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AM29F100B-120FCB Datasheet(PDF) 2 Page - Advanced Micro Devices |
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AM29F100B-120FCB Datasheet(HTML) 2 Page - Advanced Micro Devices |
2 / 36 page 2 Am29F100 GENERAL DESCRIPTION The Am29F100 is a 1 Mbit, 5.0 Volt-only Flash memory organized as 131,072 bytes or 65,536 words. The Am29F100 is offered in 44-pin SO and 48-pin TSOP packages. Word-wide data appears on DQ0-DQ15; byte-wide data on DQ0-DQ7. The device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed or erased in standard EPROM program- mers. The standard device offers access times of 70, 90, 120, and 150 ns, allowing high-speed microproces- sors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power sup- ply for both read and write functions. Internally gener- ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Com- mands are written to the command register using stan- dard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the pro- gramming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This invokes the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase com- mand sequence. This invokes the Embedded Erase algorithm—an internal algorithm that automatically pre- programs the array (if it is not already programmed) be- fore executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The Erase Suspend feature enables the system to put erase on hold for any period of time to read data from, or program data to, a sector that is not being erased. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is erased when shipped from the factory. The hardware data protection measures include a low VCC detector automatically inhibits write operations during power transitions. The hardware sector pro- tection feature disables both program and erase oper- ations in any combination of the sectors of memory, and is implemented using standard EPROM program- mers. The temporary sector unprotect feature allows in-system changes to protected sectors. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highes t lev e ls of qualit y, re liabilit y, and c o s t effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. |
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