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ST62T25LD3 Datasheet(PDF) 73 Page - STMicroelectronics |
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ST62T25LD3 Datasheet(HTML) 73 Page - STMicroelectronics |
73 / 105 page ST6215C ST6225C 73/105 11.5 CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for VDD, fOSC, and TA. 11.5.1 General Timings 11.5.2 External Clock Source Notes: 1. Data based on typical application software. 2. Time measured between interrupt event and interrupt vector fetch. Δt c(INST) is the number of tCPU cycles needed to finish the current instruction execution. Figure 49. Typical Application with an External Clock Source Symbol Parameter Conditions Min Typ 1) Max Unit tc(INST) Instruction cycle time 24 5 tCPU fCPU=8 MHz 3.25 6.5 8.125 μs tv(IT) Interrupt reaction time 2) tv(IT) = Δtc(INST) + 6 611 tCPU fCPU=8 MHz 9.75 17.875 μs Symbol Parameter Conditions Min Typ Max Unit VOSCINH OSCIN input pin high level voltage See Figure 49 0.7xVDD VDD V VOSCINL OSCIN input pin low level voltage VSS 0.3xVDD IL OSCx Input leakage current VSS≤VIN≤VDD ± 2 μA OSCIN OSCOUT fOSC EXTERNAL ST62XX CLOCK SOURCE VOSCINL VOSCINH IL 90% 10% Not connected 1 |
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