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74AUP1G32GX Datasheet(PDF) 3 Page - NXP Semiconductors |
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74AUP1G32GX Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 21 page 74AUP1G32 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 7 — 8 July 2013 3 of 21 NXP Semiconductors 74AUP1G32 Low-power 2-input OR-gate 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 4. Pin configuration SOT353-1 Fig 5. Pin configuration SOT886 74AUP1G32 BVCC A GND Y 001aaf028 1 2 3 5 4 74AUP1G32 A 001aaf029 B GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 Fig 7. Pin configuration SOT1226 (X2SON5) 74AUP1G32 A 001aaf030 B GND n.c. VCC Y Transparent top view 2 3 1 5 4 6 B VCC GND 1 3 2 5 4 A Y aaa-003004 Transparent top view 74AUP1G32 Table 3. Pin description Symbol Pin Description TSSOP5 and X2SON5 XSON6 B 1 1 data input A 2 2 data input GND 3 3 ground (0 V) Y 4 4 data output n.c. - 5 not connected VCC 5 6 supply voltage |
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