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TPIC44L02DBG4 Datasheet(PDF) 2 Page - Texas Instruments

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No. de Pieza. TPIC44L02DBG4
Descripción  4-CHAMMEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
Descarga  24 Pages
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Fabricante  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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TPIC44L02DBG4 Datasheet(HTML) 2 Page - Texas Instruments

 
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TPIC44L01, TPIC44L02, TPIC44L03
4CHANNEL SERIAL AND PARALLEL LOW SIDE PREFET DRIVER
SLIS062B NOVEMBER 1996 – REVISED AUGUST 2001
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must
consist of at least four bits of data. In applications where multiple devices are cascaded together, the string of
data must consist of four bits for each device. A high data bit turns the respective output channel on and a low
data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device.
Fault data consists of fault flags for shorted-load and open-load flags (bits 0–3) for each of the four output
channels. A high bit in the fault data indicates a fault and a low bit indicates that no fault is present for that
channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault
must be present when CS is transitioned from high to low to be captured and reported in the serial fault data.
New faults cannot be captured in the serial register when CS is low. CS must be transitioned high after all of
the serial data has been clocked into the device. A low-to-high transition of CS transfers the last four bits of serial
data to the output buffer puts SDO in a high-impedance state and clears and reenables the fault register. The
TPIC44L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded
together to simplify the serial interface to the controller. Serial input data flows through the device and is
transferred out SDO following the fault data in cascaded configurations.
For parallel operation, data is transferred directly from the parallel input interface IN0-IN3 to the respective
GATE(0–3) output asynchronously. SCLK or CS is not required for parallel control. A 1 on the parallel input turns
the respective channel on, where a 0 turns it off. Note that either the serial input interface or the parallel input
interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data
interface.
The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions
in the the on and off states respectively. These devices offer the option of using an internally generated
fault-reference voltage or an externally supplied fault-reference voltage through VCOMP for fault detection. The
internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by
connecting VCOMPEN to VCC. The drain voltage is compared to the fault reference when the channel is turned
on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted
fault occurs using the TPIC44L01 or the TPIC44L03, the channel is turned off and a fault flag is sent to the control
device as well as to the serial fault register bits. If a fault occurs while using the TPIC44L02, the channel
transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present.
Shorted-load fault conditions must be present for at least the shorted-load deglitch time, t(STBDG), to be flagged
as a fault. A fault flag is sent to the control device as well as the serial fault register bits. More detail on fault
detection operation is presented in the device operation section of this data sheet.
These devices provide protection from over-battery voltage and under-battery voltage conditions irrespective
of the state of the output channels. When the battery voltage is greater than the overvoltage threshold or less
than the undervoltage threshold, all channels are disabled and a fault flag is generated. Battery-voltage faults
are not reported in the serial fault data. The outputs return to normal operation once the battery-voltage fault
has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the
battery fault, but disables fault reporting for open- and shorted-load conditions. Fault reporting for open- and
shorted-load conditions are reenabled after the battery fault condition has been corrected.
These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect
the FET. The clamp voltage is defined by the sum of VCC and turnon voltage of the external FET. The predriver
also provides a gate-to-source voltage (VGS) clamp to protect the gate-source terminals of the power FET from
exceeding their rated voltages. An external active low RESET is provided to clear all registers and flags in the
device. GATE(0–3) outputs are disabled after RESET has been pulled low.
These devices provide pulldown resistors on all inputs except CS and RESET. A pullup resistor is used on CS
and RESET.


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