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ADS7816PCG4 Datasheet(PDF) 10 Page - Texas Instruments |
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ADS7816PCG4 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 24 page 10 ® ADS7816 D OUT 1.4V Test Point 3k Ω 100pF C LOAD t r D OUT V OH V OL t f t dDO t hDO D OUT DCLOCK V OH V OL V IL D OUT Test Point t dis Waveform 2, ten t dis Waveform 1 100pF C LOAD 3k Ω t dis CS/SHDN DOUT Waveform 1(1) DOUT Waveform 2(2) 90% 10% V IH 1 B11 2 t en CS/SHDN DCLOCK V OL D OUT V CC Load Circuit for tdDO, tr, and tf Voltage Waveforms for DOUT Rise and Fall TImes tr, and tf Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and tden Voltage Waveforms for ten FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I. Voltage Waveforms for tdis DESCRIPTION ANALOG VALUE Full Scale Range VREF Least Significant VREF/4096 Bit (LSB) Full Scale VREF –1 LSB 1111 1111 1111 FFF Midscale VREF/2 1000 0000 0000 800 Midscale – 1 LSB VREF/2 – 1 LSB 0111 1111 1111 7FF Zero 0V 0000 0000 0000 000 Table II. Ideal Input Voltages and Output Codes. DIGITAL OUTPUT: STRAIGHT BINARY BINARY CODE HEX CODE NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. DATA FORMAT The output data from the ADS7816 is in Straight Binary format as shown in Table II. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. POWER DISSIPATION The architecture of the converter, the semiconductor fabrica- tion process, and a careful design allow the ADS7816 to convert at up to a 200kHz rate while requiring very little power. Still, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS7816 scales directly with conversion rate. The first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. In addition, the ADS7816 is in power down mode under two conditions: when the conversion is complete and whenever CS is HIGH (see Figure 1). Ideally, each conversion should occur as quickly as possible, preferably, at a 3.2MHz clock rate. This way, the converter spends the longest possible time in the power down mode. This is very important as the |
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