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LM5070SD-80 Datasheet(PDF) 3 Page - Texas Instruments

No. de pieza LM5070SD-80
Descripción Electrónicos  LM5070 Integrated Power Over Ethernet PD Interface and PWM Controller
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Fabricante Electrónico  TI [Texas Instruments]
Página de inicio  http://www.ti.com
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LM5070SD-80 Datasheet(HTML) 3 Page - Texas Instruments

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LM5070
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SNVS308G – OCTOBER 2004 – REVISED APRIL 2013
PIN DESCRIPTIONS
Pin
Name
Description
Application Information
1
VIN
System high potential input.
The diode “OR” of several lines entering the PD, it is the more positive
input potential.
2
RSIG
Signature resistor pin.
Connect a 25k
Ω signature resistor from VIN to this pin for signature
detection.
3
RCLASS
Classification resistor pin.
Connect the classification programming resistor from this pin to VEE.
4
UVLO
Line under-voltage lockout.
An external resistor divider from VIN to UVLORTN programs the
shutdown levels with a 2.00V threshold at the UVLO pin. Hysteresis is
set by a switched internal 10uA current source that forces additional
current into the resistor divider.
5
UVLORTN
Return for the external UVLO resistors.
Connect the bottom resistor of the resistor divider between the UVLO
pin and this pin.
6
RCLP
Current limit programming pin.
Programs the inrush current limit for the device. If left open, the inrush
current limit will default to 400mA max.
7
VEE
System low potential input.
Diode “OR’d” to the RJ45 connector and PSE’s –48V supply, it is the
more negative input potential.
8
RTN
System return for the PWM converter.
The drain of the internal current limiting power MOSFET which
connects VEE to the return path of the dc-dc converter.
9
OUT
Output of the PWM controller.
DC-DC converter gate driver output with 800mA peak sink current
capability.
10
VCC
Output of the internal high voltage series
When the auxiliary transformer winding (if used) raises the voltage on
pass regulator. Regulated output voltage is
this pin above the regulation set point, the internal series pass regulator
nominally 7.8V.
will shutdown, reducing the controller power dissipation.
11
FB
Feedback signal.
Inverting input of the internal error amplifier. The non-inverting input is
internally connected to a 1.25V reference.
12
COMP
The output of the error amplifier and input
COMP pull-up is provided by an internal 5K resistor which may be used
to the Pulse Width Modulator.
to bias an opto-coupler transistor.
13
CS
Current sense input.
Current sense input for current mode control and over-current
protection. Current limiting is accomplished using a dedicated current
sense comparator. If the CS pin voltage exceeds 0.5V the OUT pin
switches low for cycle-by-cycle current limiting. CS is held low for 50ns
after OUT switches high to blank leading edge current spikes.
14
RT / SYNC
Oscillator timing resistor pin and
An external resistor connected from RT to ARTN sets the oscillator
synchronization input.
frequency. This pin will also accept narrow ac-coupled synchronization
pulses from an external clock.
15
SS
Soft-start input.
An external capacitor and an internal 10uA current source set the soft-
start ramp rate.
16
ARTN
Analog PWM supply return.
RTN for sensitive analog circuitry including the SMPS current limit
amplifier.
EP
Exposed PAD, underside of the WSON
Internally bonded to the die substrate. Connect to VEE potential for low
package option.
thermal impedance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2004–2013, Texas Instruments Incorporated
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