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TPS70251 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS70251 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 37 page TPS70245, TPS70248 TPS70251, TPS70258 TPS70202 SLVS286E – JUNE 2000 – REVISED DECEMBER 2009 www.ti.com The TPS702xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have extremely low noise output performance without using any added filter bypass capacitors and are designed to have a fast transient response and be stable with 10 μF low ESR capacitors. These devices have fixed 3.3V/2.5V, 3.3V/1.8V, 3.3V/1.5V, 3.3V/1.2V, and adjustable voltage options. Regulator 1 can support up to 500mA, and regulator 2 can support up to 250mA. Separate voltage inputs allow the designer to configure the source power. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 μA over the full range of output current and full range of temperature). This LDO family also features a sleep mode; applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2 μA at TJ = +25°C. For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator is turned off (disabled). The PG1 pin reports the voltage condition at VOUT1. The PG1 pin can be used to implement a SVS (RESET, POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at VOUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2. The TPS702xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event of an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the logic high state, RESET goes to a high impedance state after a 120ms delay. To monitor VOUT1, the PG1 output pin can be connected to MR. To monitor VOUT2, the PG2 output pin can be connected to MR. The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until VIN1 reaches 2.5V. 2 Submit Documentation Feedback Copyright © 2000–2009, Texas Instruments Incorporated |
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