Rev. F

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Page 30 of 64

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March 2008

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Multiprocessor Bus Request and Host Bus Request

Use these specifications for passing of bus mastership between

multiprocessing ADSP-2106xs (BRx) or a host processor, both

synchronous and asynchronous (HBR, HBG).

Table 18. Multiprocessor Bus Request and Host Bus Request

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

HBG Low to RD/WR/CS Valid1

20 + 5DT/4

ns

HBR Setup Before CLKIN2

20 + 3DT/4

ns

HBR Hold After CLKIN2

14 + 3DT/4

ns

HBG Setup Before CLKIN

13 + DT/2

ns

HBG Hold After CLKIN High

6 + DT/2

ns

BRx, CPA Setup Before CLKIN3

13 + DT/2

ns

BRx, CPA Hold After CLKIN High

6 + DT/2

ns

RPBA Setup Before CLKIN

21 + 3DT/4

ns

RPBA Hold After CLKIN

12 + 3DT/4

ns

Switching Characteristics

HBG Delay After CLKIN

7 – DT/8

ns

HBG Hold After CLKIN

–2 – DT/8

ns

BRx Delay After CLKIN

7 – DT/8

ns

BRx Hold After CLKIN

–2 – DT/8

ns

CPA Low Delay After CLKIN4

8 – DT/8

ns

CPA Disable After CLKIN

–2 – DT/8

4.5 – DT/8

ns

REDY (O/D) or (A/D) Low from CS and HBR Low5, 6

8.5

ns

REDY (O/D) Disable or REDY (A/D) High from HBG6, 7

44 + 23DT/16

ns

REDY (A/D) Disable from CS or HBR High6

10

ns

easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the ADSP-2106x SHARC

User’s Manual, Revision 2.1.