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ATMEGA163 Datasheet(PDF) 47 Page - ATMEL Corporation

No. de pieza ATMEGA163
Descripción Electrónicos  8-bit Microcontroller with 16K Bytes In-System Programmable Flash
Download  187 Pages
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Fabricante Electrónico  ATMEL [ATMEL Corporation]
Página de inicio  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATMEGA163 Datasheet(HTML) 47 Page - ATMEL Corporation

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ATmega163(L)
1142E–AVR–02/03
TCNT1 Timer/Counter1 Write
When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP
Register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined
with the byte data in the TEMP Register, and all 16 bits are written to the TCNT1
Timer/Counter1 Register simultaneously. Consequently, the high byte TCNT1H must be
accessed first for a full 16-bit register write operation.
TCNT1 Timer/Counter1 Read
When the CPU reads the low byte TCNT1L, the data of the Low Byte TCNT1L is sent to
the CPU and the data of the High Byte TCNT1H is placed in the TEMP Register. When
the CPU reads the data in the High Byte TCNT1H, the CPU receives the data in the
TEMP Register. Consequently, the Low Byte TCNT1L must be accessed first for a full
16-bit register read operation.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read
and write access. If Timer/Counter1 is written to and a clock source is selected, the
Timer/Counter1 continues counting in the timer clock cycle after it is preset with the writ-
ten value.
Timer/Counter1 Output
Compare Register – OCR1AH
and OCR1AL
Timer/Counter1 Output
Compare Register – OCR1BH
and OCR1BL
The Output Compare Registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously
compared with Timer/Counter1. Actions on compare matches are specified in the
Timer/Counter1 Control and Status Register. A software write to the Timer/Counter
Register blocks compare matches in the next Timer/Counter clock cycle. This prevents
immediate interrupts when initializing the Timer/Counter.
A Compare Match will set the compare interrupt flag in the CPU clock cycle following the
compare event.
Since the Output Compare Registers – OCR1A and OCR1B – are 16-bit registers, a
temporary register TEMP is used when OCR1A/B are written to ensure that both bytes
are updated simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH,
the data is temporarily stored in the TEMP Register. When the CPU writes the Low Byte,
OCR1AL or OCR1BL, the TEMP Register is simultaneously written to OCR1AH or
OCR1BH. Consequently, the high byte OCR1AH or OCR1BH must be written first for a
full 16-bit register write operation.
Bit
15141312
1110
9
8
$2B ($4B)
MSB
OCR1AH
$2A ($4A)
LSB
OCR1AL
76543
210
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
00000
000
00000
000
Bit
15141312
1110
9
8
$29 ($49)
MSB
OCR1BH
$28 ($48)
LSB
OCR1BL
76543
210
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
00000
000
00000
000


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