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ADS1210U Datasheet(PDF) 2 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
No. de pieza ADS1210U
Descripción Electrónicos  24-Bit ANALOG-TO-DIGITAL CONVERTER
Download  41 Pages
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Fabricante Electrónico  BURR-BROWN [Burr-Brown (TI)]
Página de inicio  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

ADS1210U Datasheet(HTML) 2 Page - Burr-Brown (TI)

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ADS1210, 1211
®
All specifications TMIN to TMAX, AVDD = DVDD = +5V, fXIN = 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REFOUT disabled,VBIAS disabled,
and external 2.5V reference, unless otherwise specified.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
SPECIFICATIONS
ADS1210U, P/ADS1211U, P, E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range(1)
0+5
V
With VBIAS(2)
–10
+10
V
Input Impedance
G = Gain, TMR = Turbo Mode Rate
4/(G • TMR)(3)
M
Programmable Gain Amplifier
User Programmable: 1, 2, 4, 8, or 16
1
16
Input Capacitance
8pF
Input Leakage Current
At +25
°C5
50
pA
At TMIN to TMAX
1nA
SYSTEMS PERFORMANCE
Resolution
24
Bits
No Missing Codes
fDATA = 60Hz
22
Bits
Integral Linearity
fDATA = 60Hz
±0.0015
%FSR
fDATA = 1000Hz, TMR of 16
±0.0015
%FSR
Unipolar Offset Error(4)
See Note 5
Unipolar Offset Drift(6)
1
µV/°C
Gain Error(4)
See Note 5
Gain Error Drift(6)
1
µV/°C
Common-Mode Rejection(9)
At DC, +25
°C
100
115
dB
At DC, TMIN to TMAX
90
115
dB
50Hz, fDATA = 50Hz(7)
160
dB
60Hz, fDATA = 60Hz(7)
160
dB
Normal-Mode Rejection
50Hz, fDATA = 50Hz(7)
100
dB
60Hz, fDATA = 60Hz(7)
100
dB
Output Noise
See Typical Performance Curves
Power Supply Rejection
DC, 50Hz, and 60Hz
65
dB
VOLTAGE REFERENCE
Internal Reference (REFOUT)
2.4
2.5
2.6
V
Drift
25
ppm/
°C
Noise
50
µVp-p
Load Current
Source or Sink
1
mA
Output Impedance
2
External Reference (REFIN)
2.0
3.0
V
Load Current
2.5
µA
VBIAS Output
Using Internal Reference
3.15
3.3
3.45
V
Drift
50
ppm/
°C
Load Current
Source or Sink
10mA
DIGITAL INPUT/OUTPUT
Logic Family
TTL Compatible CMOS
Logic Level: (all except XIN)
VIH
IIH = +5µA
2.0
DVDD +0.3
V
VIL
IIL = +5µA
–0.3
0.8
V
VOH
IOH = 2 TTL Loads
2.4
V
VOL
IOL = 2 TTL Loads
0.4
V
XIN Input Levels: VIH
3.5
DVDD +0.3
V
VIL
–0.3
0.8
V
XIN Frequency Range (fXIN)
0.5
10
MHz
Output Data Rate (fDATA)
User Programmable
2.4
15,625
Hz
fXIN = 500kHz
0.12
781
Hz
Data Format
User Programmable
Two’s Complement
or Offset Binary
SYSTEM CALIBRATION
Offset and Full-Scale Limits
VFS = Full-Scale Differential Voltage(8)
0.7 • (2 • REFIN)/G
VFS – | VOS |VOS = Offset Differential Voltage(8)
1.3 • (2 • REFIN)/G


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