®

ADS7809

5

FIGURE 1. Basic Conversion Timing.

MODE Acquire

t

4

t

5

t

1

t

3

t

7

t

6

Convert

Acquire

t

2

BUSY

CS, R/C

+85

°C.

FIGURE 2. Serial Data Timing Using Internal Clock. (CS, EXT/INT and TAG Tied LOW.)

SYMBOL

DESCRIPTION

MIN

TYP MAX UNITS

Convert Pulse Width

40

6000

ns

BUSY Delay

65

ns

BUSY LOW

8

µs

BUSY Delay after

220

ns

End of Conversion

Aperture Delay

40

ns

Conversion Time

7.6

8

µs

Acquisition Time

2

µs

Throughput Time

9

10

µs

R/C LOW to DATACLK Delay

450

ns

DATACLK Period

440

ns

Data Valid to DATACLK

20

75

ns

HIGH Delay

Data Valid after

100

125

ns

DATACLK LOW Delay

External DATACLK

100

ns

External DATACLK HIGH

20

ns

External DATACLK LOW

30

ns

DATACLK HIGH

20

ns

Setup Time

R/C to CS Setup Time

10

ns

SYNC Delay After

15

35

ns

DATACLK HIGH

Data Valid Delay

25

55

ns

CS to Rising Edge Delay

25

ns

Data Available after CS LOW

6

µs

1

MSB Valid

R/C

DATACLK

SDATA

t

8

t

11

t

10

t

9

2

3

15

16

Bit 14 Valid

Bit 1 Valid

Bit 13 Valid

LSB Valid

t

2

t

3

BUSY

t

1