10

®

ADS7812

INTERNAL DATACLK

With EXT/INT tied LOW, the result from conversion ‘n’ is

serially transmitted during conversion ‘n+1’, as shown in

Figure 5 and with the timing given in Table II. Serial

transmission of data occurs only during a conversion. When

a transmission is not in progress, DATA and DATACLK are

LOW.

During the conversion, the results of the previous conver-

sion will be transmitted via DATA, while DATACLK

provides the synchronous clock for the serial data. The data

format is 12-bit, Binary Two’s Complement, and MSB first.

Each data bit is valid on both the rising and falling edges of

DATACLK. BUSY is LOW during the entire serial trans-

mission and can be used as a frame synchronization signal.

EXTERNAL DATACLK

With EXT/INT tied HIGH, the result from conversion ‘n’ is

clocked out after the conversion has completed, during the

next conversion (‘n+1’), or a combination of these two.

Figure 6 shows the case of reading the conversion result

after the conversion is complete. Figure 7 describes reading

the result during the next conversion. Figure 8 combines the

important aspects of Figures 6 and 7 as to reading part of the

result after the conversion is complete and the remainder

during the next conversion.

The serial transmission of the conversion result is initiated

by a rising edge on DATACLK. The data format is 12-bit,

Binary Two’s Complement, and MSB first. Each data bit is

valid on the falling edge of DATACLK. In some cases, it

t

17

DATACLK

BUSY

CONV

t

1

t

12

t

18

t

16

t

14

t

13

t

15

1

1

2

3

10

11

12

DATA

MSB

Bit 10

Bit 9

Bit 2

Bit 1

LSB

MSB

BUSY

CONV

t

1

t

5

DATACLK

t

4

t

23

t

22

t

21

t

20

t

19

1234

10

11

12

DATA

MSB

Bit 10

Bit 9

Bit 2

Bit 1

LSB

FIGURE 5. Serial Data Timing, Internal Clock (EXT/INT and CS LOW).

FIGURE 6. Serial Data Timing, External Clock, Clocking After the Conversion Completes (EXT/INT HIGH, CS LOW).