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ADS7842E Datasheet(PDF) 11 Page - Burr-Brown (TI) |
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ADS7842E Datasheet(HTML) 11 Page - Burr-Brown (TI) |
11 / 13 page ® 11 ADS7842 FIGURE 2. Normal Operation, 16 Clocks per Conversion. CS RD WR BUSY A0 A1 COMMENTS 0 X 11X Power Down Mode 0 X 10X Wake Up Mode means rising edge triggered. X = Don't care. TABLE III. Truth Table for Power Down and Wake Up Modes. FIGURE 3. Initiating a Conversion. 12 3 CS WR BUSY RD A0 A1 CLK Latching in Address for Next Channel Conversion 45 67 8 9 10 1112 13 14 1516 Sample DATA VALID DB0-DB11 DIGITAL OUTPUT STRAIGHT BINARY DESCRIPTION ANALOG INPUT BINARY CODE HEX CODE Least Significant Bit (LSB) 1.2207mV Full Scale 4.99878V 1111 1111 1111 FFF Midscale 2.5V 1000 0000 0000 800 Midscale –1LSB 2.49878V 0111 1111 1111 7FF Zero Full Scale 0V 0000 0000 0000 000 Table IV. Ideal Input Voltages and Output Codes (VREF = 5V). CS WR CLK BUSY A0, A1 t 1 t 5 t 2 t 10 t 9 t 3 t 4 t 6 t 8 t 7 N + 1(1) NOTE: (1) Addresses for next conversion (N + 1) latched in with rising edge of current WR (N). t CKL |
Número de pieza similar - ADS7842E |
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Descripción similar - ADS7842E |
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