11

®

ADS824

the resistive reference ladder. The bandgap reference circuit

includes logic functions that allows setting the analog input

swing of the ADS824 to either a 1Vp-p or 2Vp-p full-scale

range by simply tying the RSEL pin to a Low or High

potential, respectively. While operating the ADS824 in the

external reference mode, the buffer amplifiers for the REFT

and REFB are disconnected from the reference ladder.

As shown, the ADS824 has internal 50k

Ω pull-up resistors

at the range select pin (RSEL) and reference select pin

(INT/EXT). Leaving these pins open configures the ADS824

for a 2Vp-p input range and external reference operation.

Setting the ADS824 up for internal reference mode requires

to bringing the INT/EXT pin low.

The reference buffers can be utilized to supply up to 1mA

(sink and source) to external circuitry. The resistor ladder of

the ADS824 is divided into several segments and has two

additional nodes, ByT and ByB, which are brought out for

external bypassing only (Figure 6). To ensure proper opera-

tion with any reference configurations, it is necessary to

provide solid bypassing at all reference pins in order to keep

the clock feedthrough to a minimum. All bypassing capaci-

tors should be located as close to their respective pins as

possible.

The common-mode voltage available at the CM-pin may be

used as a bias voltage to provide the appropriate offset for

the driving circuitry. However, care must be taken not to

appreciably load this node, which is not buffered and has a

high impedance. An alternative way of generating a com-

mon-mode voltage is given in Figure 7. Here, two external

precision resistors (tolerance 1% or better) are located

between the top and bottom reference pins. The common-

mode voltage, CMV, will appear at the midpoint.

EXTERNAL REFERENCE OPERATION

For even more design flexibility, the internal reference can

be disabled and an external reference voltage be used. The

utilization of an external reference may be considered for

applications requiring higher accuracy, improved tempera-

ture performance, or a wide adjustment range of the

converter’s full-scale range. Especially in multichannel

applications, the use of a common external reference has the

benefit of obtaining better matching of the full-scale range

between converters.

The external references can vary as long as the value of the

See Figure 8.

DIGITAL INPUTS AND OUTPUTS

Clock Input Requirements

Clock jitter is critical to the SNR performance of high speed,

high resolution A/D converters. Clock jitter leads to aperture

ADS824 samples the input signal on the rising edge of the

CLK input. Therefore, this edge should have the lowest

possible jitter. The jitter noise contribution to total SNR is

FIGURE 8. Configuration Example for External Reference Operation.

FIGURE 7. Alternative Circuit to Generate CM Voltage.

REFT

+3.5V

ADS824

CMV

+2.5V

REFB

+1.5V

R

1

1.0k

Ω

R

2

1.0k

Ω

0.1

µF

0.1

µF

ADS824

IN

IN

INT/EXT

REFT

ByT

GND

ByB

REFB

4 x 0.1µF || 2.2µF

External Top Reference

REFT = REFB +0.8V to +3.75V

+VS

BA

RSEL

GND

+5V

External Bottom Reference

REFB = REFT –0.8V to +1.25V

V

IN

A - Short for 1Vp-p Input Range

B - Short for 2Vp-p Input Range (Default)

CMV

+2.5V

DC