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ADS8344 Datasheet(PDF) 10 Page - Burr-Brown (TI) |
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ADS8344 Datasheet(HTML) 10 Page - Burr-Brown (TI) |
10 / 13 page ® 10 ADS8344 inputs provide a differential input. See Tables I and II and Figure 2 for more information. The last two bits (PD1 - PD0) select the power-down mode and clock mode as shown in Table V. If both PD1 and PD0 are HIGH, the device is always powered up. If both PD1 and PD0 are low, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly—no delay is needed to allow the device to power up and the very first conversion will be valid. Clock Modes The ADS8344 can be used with an external serial clock or an internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the device. Internal clock mode is selected when PD1 is HIGH and PD0 is LOW. External Clock Mode In external clock mode, the external clock not only shifts data in and out of the ADS8344, it also controls the A/D conversion steps. BUSY will go HIGH for one clock period after the last bit of the control byte is shifted in. Successive- approximation bit decisions are made and appear at DOUT on each of the next 16 SCLK falling edges (Figure 3). Figure 4 shows the BUSY timing in external clock mode. FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port. t ACQ Acquire Idle Conversion 1 DCLK CS 81 15 DOUT BUSY (MSB) (START) (LSB) A2 S DIN A1 A0 SGL/ DIF PD1 PD0 14 13 12 11 10 9 8 7654321 0 Zero Filled... 81 8 Acquire Idle Conversion 18 1 15 (MSB) (START) A2 SA1 A0 SGL/ DIF PD1 PD0 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (MSB) (LSB) S A2 A1 A0 — SGL/DIF PD1 PD0 TABLE III. Order of the Control Bits in the Control Byte. TABLE IV. Descriptions of the Control Bits within the Control Byte. BIT NAME DESCRIPTION 7 S Start Bit. Control byte starts with first HIGH bit on DIN. 6 - 4 A2 - A0 Channel Select Bits. Along with the SGL/DIF bit, these bits control the setting of the multiplexer input as detailed in Tables I and II. 2 SGL/DIF Single-Ended/Differential Select Bit. Along with bits A2 - A0, this bit controls the setting of the multiplexer input as detailed in Tables I and II. 1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for details. PD0 PD1 Description 0 0 Power-down between conversions. When each conversion is finished, the converter enters a low power mode. At the start of the next conversion, the device instantly powers up to full power. There is no need for additional delays to assure full operation and the very first conversion is valid. 0 1 Internal clock mode. 1 0 Reserved for future use. 1 1 No power-down between conversions, device al- ways powered. TABLE V. Power-Down Selection. FIGURE 4. Detailed Timing Diagram. PD0 t BDV t DH t CH t CL t DS t CSS t DV t BD t BD t TR t BTR t D0 t CSH DCLK CS 15 DOUT BUSY DIN 14 |
Número de pieza similar - ADS8344 |
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Descripción similar - ADS8344 |
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