®

5

DAC7611

TIMING DIAGRAMS

LOGIC TRUTH TABLE

SERIAL SHIFT

CLR

LD

REGISTER

DAC REGISTER

H

X

H

H

No Change

No Change

L

L

H

H

No Change

No Change

L

H

H

H

No Change

No Change

L

↑

H

H

Advanced One Bit

No Change

↑

L

H

H

Advanced One Bit

No Change

XH

↓

No Change

Changes to Value of

Serial Shift Register

XH

No Change

Transparent

H

X

L

X

No Change

HX

↑

H

No Change

↑ Positive Logic Transition; ↓ Negative Logic Transition; X = Don’t Care.

NOTES: (1) CS and CLK are interchangeable. (2) A HIGH value is suggested

in order to avoid to “false clock” from advancing the shift register and changing

the DAC voltage. (3) If data is clocked into the serial register while LD is LOW,

the DAC output voltage will change, reflecting the current value of the serial

shift register.

TIMING SPECIFICATIONS

SYMBOL

DESCRIPTION

MIN

TYP

MAX UNITS

Clock Width HIGH

30

ns

Clock Width LOW

30

ns

Load Pulse Width

20

ns

Data Setup

15

ns

Data Hold

15

ns

Clear Pulse Width

30

ns

Load Setup

15

ns

Load Hold

10

ns

Select

30

ns

Deselect

20

ns

of +5V) and timed from a voltage level of 1.6V. These parameters are

guaranteed by design and are not subject to production testing.

D11

(MSB)

(LSB)

SDI

CLK

CS

LD

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

t

CSS

t

LD1

t

LD2

t

CSH

LD

FS

ZS

CLR

V

OUT

t

LDW

t

S

t

CLRW

t

S

±1 LSB

Error Band

SDI

CLK

t

CL

t

CH

t

DH

t

DS