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DAC7611P Datasheet(PDF) 5 Page - Burr-Brown (TI) |
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DAC7611P Datasheet(HTML) 5 Page - Burr-Brown (TI) |
5 / 12 page ® 5 DAC7611 TIMING DIAGRAMS LOGIC TRUTH TABLE SERIAL SHIFT CS(1) CLK(1) CLR LD REGISTER DAC REGISTER H X H H No Change No Change L L H H No Change No Change L H H H No Change No Change L ↑ H H Advanced One Bit No Change ↑ L H H Advanced One Bit No Change H(2) XH ↓ No Change Changes to Value of Serial Shift Register H(2) XH L(3) No Change Transparent H X L X No Change Loaded with 000H HX ↑ H No Change Latched with 000H ↑ Positive Logic Transition; ↓ Negative Logic Transition; X = Don’t Care. NOTES: (1) CS and CLK are interchangeable. (2) A HIGH value is suggested in order to avoid to “false clock” from advancing the shift register and changing the DAC voltage. (3) If data is clocked into the serial register while LD is LOW, the DAC output voltage will change, reflecting the current value of the serial shift register. TIMING SPECIFICATIONS TA = –40°C to +85°C and VDD = +5V. SYMBOL DESCRIPTION MIN TYP MAX UNITS tCH Clock Width HIGH 30 ns tCL Clock Width LOW 30 ns tLDW Load Pulse Width 20 ns tDS Data Setup 15 ns tDH Data Hold 15 ns tCLRW Clear Pulse Width 30 ns tLD1 Load Setup 15 ns tLD2 Load Hold 10 ns tCSS Select 30 ns tCSH Deselect 20 ns NOTE: All input control signals are specified with tR = tF = 5ns (10% to 90% of +5V) and timed from a voltage level of 1.6V. These parameters are guaranteed by design and are not subject to production testing. D11 (MSB) (LSB) SDI CLK CS LD D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 t CSS t LD1 t LD2 t CSH LD FS ZS CLR V OUT t LDW t S t CLRW t S ±1 LSB Error Band SDI CLK t CL t CH t DH t DS |
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Descripción similar - DAC7611P |
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