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CAT25C01 Datasheet(PDF) 6 Page - Catalyst Semiconductor

No. de Pieza. CAT25C01
Descripción  1K/2K/4K/8K/16K SPI Serial CMOS E2PROM
Descarga  10 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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CAT25C01 Datasheet(HTML) 6 Page - Catalyst Semiconductor

 
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CAT25C01/02/04/08/16
Doc. No. 25067-00 5/00
Advanced Information
Figure 2. WREN Instruction Timing
Figure 3. WRDI Instruction Timing
DEVICE OPERATION
Write Enable and Disable
The CAT25C01/02/04/08/16 contains a write enable
latch. This latch must be set before any write operation.
The device powers up in a write disable state when Vcc
is applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when
WP is
low and WPEN bit is set to high. The user cannot write
to the status register, (including the block protect bits
and the WPEN bit) and the block protected sections in
the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either
WP pin is high or the
WPEN bit is zero.
Note: Dashed Line= mode (1, 1) – ––––
SK
SI
CS
SO
00000
11
0
HIGH IMPEDANCE
SK
SI
CS
SO
00000
10
0
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) – ––––
writes(reset the latch) to the device. Disabling writes
will protect the device against inadvertent writes.
READ Sequence
The part is selected by pulling
CS low. The 8-bit read
instruction is transmitted to the CAT25C01/02/04/08/
16, followed by the 16-bit address for 25C08/16. (only
10-bit addresses are used for 25C08, 11-bit addresses
are used for 25C16. The rest of the bits are don't care
bits) and 8-bit address for 25C01/02/04 (for the 25C04,
bit 3 of the read data instruction contains address A8).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. The data stored in the
memory at the next address can be read sequentially by
continuing to provide clock pulses. The internal ad-
dress pointer is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to 0000h allowing the read cycle to be
continued indefinitely. The read operation is terminated
by pulling the
CS high. To read the status register,
RDSR instruction should be sent. The contents of the
status register are shifted out on the SO line. The status
register may be read at any time even during a write
cycle. Read sequece is illustrated in Figure 4. Reading
status register is illustrated in Figure 5.


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