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CAT25C32 Datasheet(PDF) 4 Page - Catalyst Semiconductor

No. de Pieza. CAT25C32
Descripción  32K/64K-Bit SPI Serial CMOS E2PROM
Descarga  9 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
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CAT25C32 Datasheet(HTML) 4 Page - Catalyst Semiconductor

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Doc. No. 25087-00 8/99 SPI-1
Advanced Information
The CAT25C32/64 supports the SPI bus data transmis-
sion protocol. The synchronous Serial Peripheral Inter-
face (SPI) helps the CAT25C32/64 to interface directly
with many of today’s popular microcontrollers. The
CAT25C32/64 contains an 8-bit instruction register.
(The instruction set and the operation codes are de-
tailed in the instruction set table)
After the device is selected with
CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
The first byte contains one of the six op-codes that define
the operation to be performed.
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25C32/64. During a read cycle,
data is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25C32/64. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge
of the SCK.
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C32/
64 and
CS high disables the CAT25C32/64. CS high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
write operation is underway). The CAT25C32/64 draws
ZERO current in the Standby mode. A high to low
transition on
CS is required prior to any sequence being
initiated. A low to high transition on
CS after a valid write
sequence is what initiates an internal write cycle.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited.
WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated,
WP going low will
have no effect on any write operation to the status
register. The
WP pin function is blocked when the WPEN
bit is set to 0.
HOLD: Hold
HOLD pin is used to pause transmission to the
CAT25C32/64 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause,
HOLD must be brought low while SCK
is low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication,
HOLD is brought
high, while SCK is low.
(HOLD should be held high any
time this function is not being used.)
HOLD may be tied
high directly to Vcc or tied to Vcc through a resistor.
Figure 9 illustrates hold timing sequence.
0000 0110
Enable Write Operations
0000 0100
Disable Write Operations
0000 0101
Read Status Register
0000 0001
Write Status Register
0000 0011
Read Data from Memory
0000 0010
Write Data to Memory

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