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CAT25C128 Datasheet(Hoja de datos) 7 Page - Catalyst Semiconductor

No. de Pieza. CAT25C128
Descripción  64K/128K-Bit SPI Serial CMOS E2PROM
Descarga  9 Pages
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Fabricante  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
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7
CAT25C64/128
Doc No. 25069-00 6/99 SPI-1
Advance Information
Figure 4. Read Instruction Timing
Byte Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the
CS low,
issuing a write instruction via the SI line, followed by the
16-bit address (the three Most Significant Bits are don’t
care for 25C64 and two most significant bits are don't
care for 25C128), and then the data to be written.
Programming will start after the
CS is brought high.
Figure 6 illustrates byte write sequence.
WRITE Sequence
The CAT25C64/128 powers up in a Write Disable state.
Prior to any write instructions, the WREN instruction
must be sent to CAT25C64/128. The device goes into
Write enable state by pulling the
CS low and then
clocking the WREN instruction into CAT25C64/128. The
CS must be brought high after the WREN instruction to
enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Figure 5. RDSR Instruction Timing
SK
SI
SO
000000
1
1
BYTE ADDRESS*
012345678
9
10
20
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
0
*Please check the instruction set table for address
CS
OPCODE
DATA OUT
MSB
HIGH IMPEDANCE
0
1
2
34
5
6
7
8
10
9
11
12
13
14
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7
6
5
4
3
2
1
0
CS
0
0
0
00
1
0
1




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