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CAT25CXXX Datasheet(PDF) 6 Page - Catalyst Semiconductor

No. de pieza CAT25CXXX
Descripción Electrónicos  Supervisory Circuits with SPI Serial E2PROM, Precision Reset Controller and Watchdog Timer
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Fabricante Electrónico  CATALYST [Catalyst Semiconductor]
Página de inicio  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT25CXXX Datasheet(HTML) 6 Page - Catalyst Semiconductor

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CAT25CXXX
Stock No. 21085-01 4/98
Advanced
The WPEN (Write Protect Enable) is an enable bit for the
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when
WP is
low and WPEN bit is set to high. The user cannot write
to the status register, (including the block protect bits
and the WPEN bit) and the block protected sections in
the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either
WP pin is high or the
WPEN bit is zero.
The watchdog timer bits, WD0 and WD1, select the
watchdog time-out period. These nonvolatile bits are
programmed with the WRSR instruction.
Status Register Bits
Array Address
Protection
BP1
BPO
Protected
0
0
None
No Protection
0
1
25C02X: C0-FF
Quarter Array Protection
25C04X: 180-1FF
25C08X: 0300-03FF
25C16X: 0600-07FF
25C32X: 0C00-0FFF
1
0
25C02X: 80-FF
Half Array Protection
25C04X: 100-1FF
25C08X: 0200-03FF
25C16X: 0400-07FF
25C32X: 0800-0FFF
1
1
25C02X: 00-FF
Full Array Protection
25C04X: 000-1FF
25C08X: 0000-03FF
25C16X: 0000-07FF
25C32X: 0000-0FFF
BLOCK PROTECTION BITS
WD1
WD0
Watchdog Timer Time-Out (Typical)
0
0
1.4 Seconds
0
1
600 Milliseconds
1
0
200 Milliseconds
1
1
Disabled
WATCHDOG TIMER BITS
Status Register
The Status Register indicates the status of the device.
The
RDY (Ready) bit indicates whether the CAT25CXXX
is busy with a write operation. When set to 1 a write cycle
is in progress and when set to 0 the device indicates it is
ready. This bit is read only.The WEL (Write Enable) bit
indicates the status of the write enable latch . When set
to 1, the device is in a Write Enable state and when set
to 0 the device is in a Write Disable state. The WEL bit
can only be set by the WREN instruction and can be
reset by the WRDI instruction.
The BPO and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowedto
protect quarter of the memory, half of the memory or the
entire memory by setting these bits. Once protectedthe
user may only read from the protected portion of the
array. These bits are non-volatile.


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