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CAT28LV64PA-30T Datasheet(PDF) 5 Page - Catalyst Semiconductor |
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CAT28LV64PA-30T Datasheet(HTML) 5 Page - Catalyst Semiconductor |
5 / 10 page CAT28LV64 5 Preliminary Doc. No. 25035-00 2/98 DEVICE UNDER TEST Vcc 1.8 K OUTPUT CL INCLUDES JIG CAPACITANCE CL= 100 pF 1. 3K INPUT PULSE LEVELS REFERENCE POINTS 2.0 V 0.6 V V - 0.3 V 0.0 V CC Figure 1. A.C. Testing Input/Output Waveform(4) Figure 2. A.C. Testing Load Circuit (example) Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) A write pulse of less than 20ns duration will not initiate a write cycle. (3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however a transition from HIGH to LOW within tBLC max. stops the timer. (4) Input rise and fall times (10% and 90%) < 10 ns. 28LV64-25 28LV64-30 28LV64-35 Symbol Parameter Min. Max. Min. Max. Min. Max. Units tWC Write Cycle Time 5 5 5 ms tAS Address Setup Time 0 0 0 ns tAH Address Hold Time 100 100 100 ns tCS CE Setup Time 0 0 0 ns tCH CE Hold Time 0 0 0 ns tCW(2) CE Pulse Time 150 150 150 ns tOES OE Setup Time 10 10 10 ns tOEH OE Hold Time 10 10 10 ns tWP(2) WE Pulse Width 150 150 150 ns tDS Data Setup Time 100 100 100 ns tDH Data Hold Time 0 0 0 ns tINIT(1) Write Inhibit Period After Power-up 5 10 5 10 5 10 ms tBLC(1)(3) Byte Load Cycle Time 0.1 100 0.1 100 0.1 100 µs 28LV64 F05 A.C. CHARACTERISTICS, Write Cycle Vcc = 3.0V to 3.6V, unless otherwise specified. 28LV64 F04 |
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