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CAT24WC17J-TE13 Datasheet(PDF) 4 Page - Catalyst Semiconductor |
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CAT24WC17J-TE13 Datasheet(HTML) 4 Page - Catalyst Semiconductor |
4 / 8 page CAT24WC03/05/09/17 4 Doc. No. 25063-00 2/98 S-1 Preliminary FUNCTIONAL DESCRIPTION The CAT24WC03/05/09/17 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. Data transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24WC03/05/ 09/17 operates as a Slave device. Both the Master and Slave devices can operate as either transmitter or re- ceiver, but the Master device controls which mode is activated. A maximum of 8 devices (24WC03), 4 devices (24WC05), 2 devices (24WC09) and 1 device (24WC17) may be connected to the bus as determined by the device address inputs A0, A1, and A2. PIN DESCRIPTIONS SCL: Serial Clock The CAT24WC03/05/09/17 serial clock input pin is used to clock all data transfers into or out of the device. This is an input pin. SDA: Serial Data/Address The CAT24WC03/05/09/17 bidirectional serial data/ad- dress pin is used to transfer data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A0, A1, A2: Device Address Inputs These inputs set device address when cascading mul- tiple devices. When these pins are left floating the default values are zeros. A maximum of eight devices can be cascaded when using 24WC03 device. All three address pins are used tWR STOP CONDITION START CONDITION ADDRESS ACK 8TH BIT BYTE n SCL SDA Figure 2. Write Cycle Timing Figure 1. Bus Timing tHIGH SCL SDA IN SDA OUT tLOW tF tLOW tR tBUF tSU:STO tSU:DAT tHD:DAT tHD:STA tSU:STA tAA tDH Figure 3. Start/Stop Timing START BIT SDA STOP BIT SCL 5020 FHD F05 5020 FHD F04 5020 FHD F03 |
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