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CAT93C5734 Datasheet(PDF) 7 Page - Catalyst Semiconductor |
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CAT93C5734 Datasheet(HTML) 7 Page - Catalyst Semiconductor |
7 / 10 page 9-91 CAT93CXXXX Stock No. 21084-01 2/98 Advanced Information Figure 2. Sychronous Data Timing SK DI CS DO tDIS tPD0,tPD1 tCSMIN tCSS tDIS tDIH tSKHI tCSH VALID VALID DATA VALID tSKLOW Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93CXXXX will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1) For the 93CXXXX, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically incre- ment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continu- ously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93CXXXX can be determined by selecting the de- vice and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Page Write The 93CXXXX writes up to 16 bytes (8 words for x16 format) of data in a single write cycle, using the page write operation. The page write operation is initiated in the same manner as the byte (word for x16 format) write operation. However, instead of terminating after the initial byte (word for x16 format) is transmitted, the host Figure 3. Read Instruction Timing SK CS DI DO HIGH-Z 11 0 AN AN–1 A0 Dummy 0 D15 . . . D0 or D7 . . . D0 1 1 1 1 1 1 1 1 1111111 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Don't Care |
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Descripción similar - CAT93C5734 |
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