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BRCG064GWZ-3 Datasheet(PDF) 21 Page - Rohm |
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BRCG064GWZ-3 Datasheet(HTML) 21 Page - Rohm |
21 / 29 page Datasheet 21/26 BRCG064GWZ-3 TSZ02201-0R2R0G100650-1-2 20.Jan.2014 Rev.001 ©2014 ROHM Co., Ltd. All rights reserved. TSZ22111・15・001 www.rohm.com Power-Up/Down Conditions At power on, the IC’s internal circuits may go through unstable low voltage area as the Vcc rises, making the IC’s internal logic circuit not completely reset, hence, malfunction may occur. To prevent this, the IC is equipped with POR circuit and LVCC circuit. To assure the operation, observe the following conditions at power on. 1. Set SDA = 'H' and SCL ='L' or 'H’ 2. Start power source so as to satisfy the recommended conditions of tR, tOFF, and Vbot for operating POR circuit. tOFF tR Vbot 0 VCC 3. Set SDA and SCL so as not to become 'Hi-Z'. When the above conditions 1 and 2 cannot be observed, take the following countermeasures. (1) In the case when the above condition 1 cannot be observed such that SDA becomes 'L' at power on. →Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'. (2) In the case when the above condition 2 cannot be observed. →After power source becomes stable, execute software reset(Page 16). (3) In the case when the above conditions 1 and 2 cannot be observed. →Carry out (1), and then carry out (2). Low Voltage Malfunction Prevention Function LVCC circuit prevents data rewrite operation at low power and prevents write error. At LVCC voltage (Typ =1.2V) or below, data rewrite is prevented. Noise Countermeasures 1. Bypass Capacitor When noise or surge gets in the power source line, malfunction may occur, therefore, it is recommended to connect a bypass capacitor (0.1µF) between the IC’s Vcc and GND pins. Connect the capacitor as close to the IC as possible. In addition, it is also recommended to attach a bypass capacitor between the board’s Vcc and GND. Recommended conditions of tR, tOFF,Vbot tR tOFF Vbot 10ms or below 10ms or larger 0.3V or below 100ms or below 10ms or larger 0.2V or below Figure 51. Rise Waveform Diagram Figure 52. When SCL= 'H' and SDA= 'L' Figure 53. When SCL='L' and SDA='L' tLOW tSU:DAT tDH After Vcc becomes stable SCL VCC SDA tSU:DAT After Vcc becomes stable |
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