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SDU06464B5B61MT-50R Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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SDU06464B5B61MT-50R Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
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8 / 12 page  Data Sheet Rev.1.0 09.04.2008 Swissbit Germany AG Wolfener Straße 36 Fon: +49 (0) 30 93 69 54 - 0 www.swissbit-germany.com Page 8 D-12681 Berlin Fax: +49 (0) 30 93 69 54 - 55 eMail: firma@swissbit-germany.com of 12 DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (0°C ≤ TA ≤ + 70°C ; V DDQ = +2.5V ± 0.2V, VDD = +2.5V ± 0.2V) see Note 1 on Page 9 AC CHARACTERISTICS 3200-3033 2700-2533 2100-2533 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX Unit Access window of DQS CK/CK# tAC -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK CL=2.0 tck (2.0) 7.5 13.0 7.5 13.0 10 13.0 CL=2.5 tck (2.5) 6.0 13.0 6.0 13.0 7.5 13.0 ns Clock cycle time CL= 3.0 tck (3.0) 5.0 13.0 ns DQ and DM input hold time relative to DQS tDH 0.40 0.45 0.5 ns DQ and DM input setup time relative to DQS tDS 0.40 0.45 0.5 ns DQ and DM input pulse width ( for each input ) tDIPW 1.75 1.75 1.75 ns Access window of DQS from CK/CK# tDQSCK -0.6 +0.6 -0.6 +0.6 -0.75 +0.75 ns DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK DQS –DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.40 0.45 0.5 ns Write command to first DQS latching transition tDQSS 0.72 1.28 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK rising- setup time tDSS 0.2 0.2 0.2 tCK DQS falling edge from CK rising- hold time tDSH 0.2 0.2 0.2 tCK Half clock period tHP tch, tcl tch, tcl tch, tcl ns Data-out high-impedance window from CK/CK# tHZ +0.7 +0.7 +0.75 ns Data-out low-impedance window from CK/CK# tLZ -0.7 -0.7 -0.75 ns Address and control input hold time ( fast slew rate ) tIHF 0.6 0.75 0.90 ns Address and control input setup time ( fast slew rate ) tISF 0.6 0.75 0.90 ns Address and control input hold time ( slow slew rate ) tIHS 0.6 0.8 1 ns Address and control input setup time ( slow slew rate ) tISS 0.6 0.8 1 ns LOAD MODE REGISTER command cycle time tMRD 10 12 15 ns Adress and control input pulse width (for each input) tIPW 2.2 2.2 2.2 ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS tHP - tQHS tHP - tQHS ns Data hold skew factor tQHS 0.5 0.6 0.75 ns |
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Descripción similar - SDU06464B5B61MT-50R |
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