Package Lead Description

PACKAGE LEAD #

LEAD SYMBOL

FUNCTION

4

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

8 Lead SO Narrow

CS5124

CS5126

11

2

-

BIAS

the IC is in sleep mode.

-

3

SYNC

Clock Synchronization Pin. A positive edge will terminate the current PWM

cycle. Ground this pin when it is not used.

3

2

UVLO

Sleep and under voltage lockout pin. A voltage greater than 1.8V causes the

chip to "wake up" however the GATE remains low. A voltage greater than

2.6V on this pin allows the output to switch.

4

4

SS

Soft Start Capacitor Pin. A capacitor placed between SS and GROUND is

charged with 10µA and discharged with 10mA. The Soft Start capacitor con-

trols both soft-start time and hiccup mode frequency.

55

Voltage Feedback Pin. The collector of an optocoupler is typically tied to this

pin. This pin is pulled up internally by a 4.3kΩ resistor to 5V and is clamped

66

Current Sense Pin. This pin is connected to the current sense resistor on the

7

7

GATE

Gate Drive Output Pin. Capable of driving a 3nF load. GATE is nominally

clamped to 13.5V.

8

8

Gnd

Ground Pin.

s

Voltage Feedback

2.9

4.3

8.1

kΩ

CS5124 Only

2.63

2.90

3.15

V

CS5126 Only

2.40

2.65

2.90

V

460

490

520

mV

s

Output Gate Drive

Maximum Sleep

1.2

2.0

V

Pull-down Voltage

GATE High (AC)

Series resistance < 1Ω (Note 1)

V

GATE Low (AC)

Series resistance < 1Ω (Note 1)

0.0

0.5

V

GATE High Clamp Voltage

11.0

13.5

16.0

V

Rise Time

Measure GATE rise time,

45

65

ns

Fall Time

Measure GATE fall time,

25

55

ns

s

Thermal Shutdown

Thermal Shutdown Temperature (Note 1) (GATE low)

135

150

165

°C

Thermal Enable Temperature

(Note 1) (GATE switching)

100

125

150

°C

Thermal Hysteresis

(Note 1)

15

25

35

°C

Notes

1. Not tested in production. Specification is guaranteed by design.