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CS8129 Datasheet(PDF) 5 Page - Cherry Semiconductor Corporation

No. de pieza CS8129
Descripción Electrónicos  5V, 750mA Low Dropout Linear Regulator with Lower RESET Threshold
Download  8 Pages
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Fabricante Electrónico  CHERRY [Cherry Semiconductor Corporation]
Página de inicio  http://www.cherrycorp.com/
Logo CHERRY - Cherry Semiconductor Corporation

CS8129 Datasheet(HTML) 5 Page - Cherry Semiconductor Corporation

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The CS8129
function has hysteresis on both the
reset and delay comparators, a latching Delay capacitor
discharge circuit, and operates down to 1V.
The
circuit output is an open collector type with
ON and OFF parameters as specified. The
output
NPN transistor is controlled by the two circuits described
(see Block Diagram).
This circuit monitors output voltage, and when output
voltage is below the specified minimum causes the
output transistor to be in the ON (saturation)
state. When the output voltage is above the specified level,
this circuit permits the
output transistor to go into
the OFF state if allowed by the
Delay circuit.
This circuit provides a programmable (by external capaci-
tor) delay on the
output lead. The Delay lead pro-
vides source current to the external delay capacitor only
when the "Low Voltage Inhibit" circuit indicates that out-
put voltage is above VRT(ON). Otherwise, the Delay lead
sinks current to ground (used to discharge the delay
capacitor). The discharge current is latched ON when the
output voltage is below VRT(OFF). The Delay capacitor is
fully discharged anytime the output voltage falls out of
regulation, even for a short period of time. This feature
ensures a controlled
pulse is generated following
detection of an error condition. The circuit allows
the
output transistor to go to the OFF (open) state
only when the voltage on the Delay lead is higher than
VDC(HI).
The Delay time for the
function is calculated from
the formula:
Delay time =
Delay time = CDelay(µF) x 3.2 x 105
If CDelay=0.1µF, Delay time (ms)=32ms ± 50%: i.e. 16ms to
48ms. The tolerance of the capacitor must be taken into
account to calculate the total variation in the delay time.
CDelay x VDelay Threshold
ICharge
RESET
RESET
RESET
RESET
Reset Delay Circuit
RESET
RESET
RESET
Low Voltage Inhibit Circuit
RESET
RESET
RESET
5
(1)
(2)
(3)
(2)
Delay
VOUT
VRT(ON)
VRT(OFF)
VRH
VDC(HI)
VDC(LO)
VDH
tDelay
VDIS
VRL
RESET
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max:
Voltage (1.0V)
RESET
Circuit Waveform
RESET
Circuit Functional Description
RESET


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