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CS4226-KQ Datasheet(PDF) 5 Page - Cirrus Logic |
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CS4226-KQ Datasheet(HTML) 5 Page - Cirrus Logic |
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5 / 60 page  CS4226 DS188F1 5 SWITCHING CHARACTERISTICS (T A = 25°C; VA+, VD+ = +5V ±5%, outputs loaded with 30 pF) Notes: 9. After powering up the CS4226, PDN should be held low until the power supply is settled. Parameter Symbol Min Typ Max Units Audio ADC's & DAC's Sample Rate Fs 4 - 50 kHz XTI Frequency (XTI = 256, 384, or 512 Fs) 1.024 - 26 MHz XTI Pulse Width High XTI = 512 Fs XTI = 384 Fs XTI = 256 Fs 10 21 31 - - - - - - ns ns ns XTI Pulse Width Low XTI = 512 Fs XTI = 384 Fs XTI = 256 Fs 10 21 31 - - - - - - ns ns ns PLL Clock Recovery Frequency RX, XTI, LRCK, LRCKAUX 30 - 50 kHz XTI Jitter Tolerance - 500 - ps PDN Low Time (Note 9) 500 - - ns SCLK Falling Edge to SDOUT Output Valid (DSCK = 0) tdpd -- ns LRCK edge to MSB valid tlrpd -- 40 ns SDIN Setup Time Before SCLK Rising Edge (DSCK=0) tds -- 25 ns SDIN Hold Time After SCLK Rising Edge (DSCK=0) tdh -- 25 ns Master Mode SCLK Period tsck -- ns SCLK Falling to LRCK Edge (DSCK=0) tmslr -±10 - ns SCLK Duty Cycle - 50 - % Slave Mode SCLK Period tsckw -- ns SCLK High Time tsckh 40 - - ns SCLK Low Time tsckl 40 - - ns SCLK Rising to LRCK Edge (DSCK=0) tlrckd 20 - - ns LRCK Edge to SCLK Rising (DSCK=0) tlrcks 40 - - ns 1 384 ()Fs -------------------- 20 + 1 256 ()Fs -------------------- 1 128 ()Fs -------------------- t mslr SCLK* SCLKAUX* (output) LRCK LRCKAUX (output) SDOUT1 SDOUT2 t sck Audio Ports Master Mode Timing sckh sckl sckw t t t MSB MSB-1 *SCLK, SCLKAUX shown for DSCK = 0 and ASCK = 0. SCLK & SCLKAUX inverted for DSCK = 1 and ASCK = 1, respectively. tdpd SDOUT1 SDOUT2 LRCKAUX (input) LRCK SCLK* SCLKAUX* (input) SDIN1 SDIN2 DATAUX dh t ds t lrpd t lrcks t lrckd t SDIN3 Audio Ports Slave Mode and Data I/O timing |
Número de pieza similar - CS4226-KQ |
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Descripción similar - CS4226-KQ |
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