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CS5126-KL Datasheet(PDF) 6 Page - Cirrus Logic |
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CS5126-KL Datasheet(HTML) 6 Page - Cirrus Logic |
6 / 32 page System Initialization Upon power up, the CS5126 must be reset to guarantee a consistent starting condition and in- itially calibrate the device. Due to the CS5126’s low power dissipation and low temperature drift, no warm-up time is required before reset to ac- commodate any self-heating effects. However, the voltage reference input should have stabi- lized to within 0.25% of its final value before RST rises to guarantee an accurate calibration. Later, the CS5126 may be reset at any time to initiate a single full calibration. Reset overrides all other functions. If reset, the CS5126 will clear and initiate a new calibration cycle mid- conversion or midcalibration. When RST is brought low all internal logic clears. When it returns high a calibration cycle begins which takes 34,584,480 master clock cy- cles to complete (approximately 1.4 seconds with a standard 24MHz master clock). The CS5126’s STBY output remains low throughout the calibration sequence, and a rising transition indicates the device is ready for normal opera- tion. A simple power-on reset circuit can be built us- ing a resistor and capacitor as shown in Fig- ure 1. The RC time constant must be long enough to guarantee the rest of the system is fully powered up and stable by the end of reset. Master Clock The CS5126 operates from an externally-sup- plied master clock. In stereo operation, the mas- ter clock frequency is set at 512 times the per- channel sampling rate (256 in 2X oversampling schemes). The CS5126 can accept master clocks up to 24.576 MHz for 48kHz stereo sampling or 96kHz monaural oversampling. All timing and control inputs for channel selec- tion, sampling, and serial data transmission may be divided down from the master clock. This yields a completely synchronous system, avoid- ing sampling and conversion errors due to asyn- chronous digital noise. CIRCUIT CONNECTIONS Stereo Operation Figure 2 shows the standard circuit connections for operating the CS5126 in its stereo mode. The HOLD, L/R, and SCLK inputs are derived from the master clock using a binary divider string. A 24.576 MHz master clock is required for a sam- pling rate of 48kHz per channel. For 48kHz stereo sampling, the CS5126 must sample and convert at a 96kHz rate to handle both channels. The master clock is divided by 256 and applied to the HOLD input. A falling transition on the HOLD pin places the input in the hold mode and initiates a conversion cycle. The HOLD input is latched internally by the master clock, so it can return high anytime after one master clock cycle plus 50ns. In stereo operation the CS5126 alternately sam- ples and converts the left and right input chan- nels. This alternating channel selection is achieved by dividing the HOLD input by two (that is, dividing the master clock by 512) and applying it to the L/R input. Upon completion of each conversion cycle, the CS5126 automatically returns to the track mode. The status of L/R as CS5126 +5V RST R C Figure 1. Power-On Reset Circuit CS5126 6 DS32F1 |
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Descripción similar - CS5126-KL |
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