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EN80C251TB24 Datasheet(PDF) 14 Page - Intel Corporation |
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EN80C251TB24 Datasheet(HTML) 14 Page - Intel Corporation |
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14 / 36 page  8xC251TB/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 8 4.0 SIGNALS Table 6. Signal Descriptions (Sheet 1 of 3) Signal Name Type Description Alternate Function A17 O 18th Address Bit (A17). Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0. See also RD# and PSEN#. P1.7/CEX4/ WCLK A16 O Address Line 16. See RD#. RD# A15:81 O Address Lines. Upper address lines for the external bus. P2.7:0 AD7:01 I/O Address/Data Lines. Multiplexed lower address lines and data lines for external memory. P0.7:0 ALE O Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus. CEX4:0 I/O Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode. P1.6:4 P1.7/A17/ WAIT# P1.3/TXD1 EA# I External Access. Directs program memory accesses to on-chip or off- chip code memory. For EA# = 0, all program memory accesses are off- chip. For EA# = 1, an access is to on-chip ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without on-chip ROM, EA# must be strapped to ground. ECI I PCA External Clock Input. External clock input to the 16-bit PCA timer. P1.2/RXD1 INT1:0# I External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0#. P3.3:2 P0.7:0 I/O Port 0. This is an 8-bit, open-drain, bidirectional I/O port. AD7:0 P1.0 P1.1 P1.2 P1.7:3 I/O Port 1. This is an 8-bit, bidirectional I/O port with internal pullups. T2 T2EX ECI/RXD1 CEX3:1 CEX4/A17/ WAIT#/ WCLK CEX0/TXD1 P2.7:0 I/O Port 2. This is an 8-bit, bidirectional I/O port with internal pullups. A15:8 P3.0 P3.1 P3.3:2 P3.5:4 P3.6 P3.7 I/O Port 3. This is an 8-bit, bidirectional I/O port with internal pullups. RXD TXD INT1:0# T1:0 WR# RD#/A16 PSEN# O Program Store Enable. Read signal output. This output is asserted for a memory address range that depends on bits RD0 and RD1 in configu- ration byte UCONFIG0 (see RD#). — |
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