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ADS5560 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS5560 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 56 page Dn_Dn+1_P Dn_Dn+1_P Dn_Dn+1_M Dn_Dn+1_M GND GND V * With external 100- termination W V OCM Logic0 V = –350mV* ODL Logic1 V =350mV* ODH T0334-01 ADS5560 ADS5562 SLWS207A – MAY 2008 – REVISED MAY 2012 www.ti.com DIGITAL CHARACTERISTICS DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level 0 or 1, AVDD = 3.0V to 3.6V, IO = 3.5 mA, RL = 100 Ω (1) (2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-level input voltage 2.4 V Low-level input voltage 0.8 V High-level input current 33 μA Low-level input current -33 μA Input capacitance 4 pF DIGITAL OUTPUTS – CMOS MODE High-level output voltage DRVDD V Low-level output voltage 0 V Output capacitance Capacitance inside the device from each output pin to 4 pF ground DIGITAL OUTPUTS – LVDS MODE VODH High-level output voltage +350 mV VODL Low-level output voltage -350 mV VOCM Output common-mode 1.2 V voltage Output capacitance Capacitance inside the device from each output pin to 4 pF ground (1) All LVDS and CMOS specifications are characterized, but not tested at production. (2) IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair. Figure 1. LVDS Output Voltage Levels 8 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): ADS5560 ADS5562 |
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