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BUF11704 Datasheet(PDF) 7 Page - Texas Instruments |
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BUF11704 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 32 page BUF12840 www.ti.com SBOS519A – OCTOBER 2010 – REVISED JULY 2011 APPLICATION INFORMATION GENERAL from a high to a low logic level while SCL is high. All slaves on the bus shift in the slave address byte on The BUF12840 programmable voltage reference the rising edge of SCL, with the last bit indicating allows fast and easy adjustment of 12 programmable whether a read or write operation is intended. During gamma reference outputs, each with 10-bit resolution. the ninth clock pulse, the slave being addressed The BUF12840 is programmed through a high-speed, responds to the master by generating an two-wire interface. The final gamma values can be Acknowledge and pulling SDA low. automatically loaded from an external EEPROM. The BUF12840 has two separate memory banks, allowing Data transfer is then initiated and eight bits of data simultaneous storage of two different gamma curves are sent, followed by an Acknowledge bit. During to facilitate dynamic switching between gamma data transfer, SDA must remain stable while SCL is curves. high. Any change in SDA while SCL is high is interpreted as a START or STOP condition. The BUF12840 can be powered using an analog supply voltage from 9V to 20V, and a digital supply Once all data have been transferred, the master from 2V to 5.5V. The digital supply must be applied generates a STOP condition, indicated by pulling before the analog supply to avoid excessive current SDA from low to high while SCL is high. The and power consumption, or possibly even damage to BUF12840 acts as a slave device after 10ms; before the device if left connected only to the analog supply that, it is the master and drives SCL and SDA. for extended periods of time. See Figure 10 for a typical configuration of the BUF12840. Note that the ADDRESSING THE BUF12840 analog power, VS, does not need to be on during any The address of the BUF12840 is 111010x, where x is interface communication. the state of the A0 pin. When the A0 pin is low, the device acknowledges on address 74h (1110100). If TWO-WIRE BUS OVERVIEW the A0 pin is high, the device acknowledges on The BUF12840 communicates over an address 75h (1110101). Table 1 shows the A0 pin industry-standard, two-wire interface to receive data settings and the BUF12840 address options. in slave mode. This model uses a two-wire, Other valid addresses are possible through a simple open-drain interface that supports multiple devices on mask change. Contact your TI representative for a single bus. Bus lines are driven to a logic low level information. only. The device that initiates the communication is called a master, and the devices controlled by the Table 1. Quick Reference of BUF12840 Addresses master are slaves. The master generates the serial BUF12840 ADDRESS ADDRESS clock on the clock signal line (SCL), controls the bus access, and generates the START and STOP A0 pin is low 1110100 (device acknowledges on address 74h) conditions. A0 pin is high To address a specific device, the master initiates a 1110101 (device acknowledges on address 75h) START condition by pulling the data signal line (SDA) Table 2. Quick Reference of Command Codes COMMAND CODE General-Call Reset Address byte of 00h followed by a data byte of 06h. 00001xxx, with SCL ≤ 400kHz; where xxx are bits unique to the Hs-capable master. This High-Speed Mode byte is called the Hs master code. Copyright © 2010–2011, Texas Instruments Incorporated 7 |
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