LM48556

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SNAS452A – JUNE 2008 – REVISED DECEMBER 2008

Figure 3. 12 Bump DSBGA - Package View

BUMP DESCRIPTIONS

Bump

Name

Description

A1

OUT-

Amplifier Inverting Output

A2

Signal Power Supply - Positive

A3

IN+

Amplifier Non-inverting Input

B1

Signal Power Supply - Negative

B2

OUT+

Amplifier Non-inverting Output

B3

IN-

Amplifier Inverting Input

C1

Charge Pump Output Voltage

C2

C1P

Charge Pump Flying Capacitor Positive Terminal

C3

SD

low to disable.

D1

C1N

Charge Pump Flying Capacitor Negative Terminal

D2

PGND

Power Ground

D3

Power Supply

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Copyright © 2008, Texas Instruments Incorporated

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