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ADC12D040 Datasheet(PDF) 10 Page - Texas Instruments

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No. de pieza ADC12D040
Descripción Electrónicos  Dual 12-Bit, 40 MSPS, 600 mW A/D Converter with Internal/External Reference
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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ADC12D040 Datasheet(HTML) 10 Page - Texas Instruments

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conversions.
ADC12D040
SNAS171D – MAY 2004 – REVISED DECEMBER 2005
www.ti.com
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =
+3.0V, PD = 0V, INT/EXT = VD, VREF = +2.0V,OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits
apply for TJ = TMIN to TMAX: all other limits TJ = 25°C
(1) (2) (3) (4)
Typical
Limits
Units
Symbol
Parameter
Conditions
(5)
(5)
(Limits)
fCLK1
Maximum Clock Frequency
40
MHz (min)
fCLK2
Minimum Clock Frequency
100
kHz
tCH
Clock High Time
9
ns
tCL
Clock Low Time
9
ns
tCONV
Conversion Latency
6
Clock Cycles
tOD
Data Output Delay after Rising CLK Edge VDR = 3.0V
10
17.5
ns (max)
tAD
Aperture Delay
1.2
ns
tAJ
Aperture Jitter
2
ps rms
tHOLD
Clock Edge to Data Transition
8
ns
tDIS
Data outputs into TRI-STATE® Mode
4
ns
tEN
Data Outputs Active after TRI-STATE®
4
ns
tPD
Power Down Mode Exit Cycle
500
ns
(1)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per (). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100
mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate
(2)
To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
(3)
With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV.
(4)
Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.
(5)
Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL
(Average Outgoing Quality Level).
Specification Definitions
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the
total time of one period. The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC.
CONVERSION LATENCY See PIPELINE DELAY.
CROSSTALK is coupling of energy from one channel into the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
10
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