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ADS7263 Datasheet(PDF) 4 Page - Texas Instruments |
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ADS7263 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 50 page ADS8363 ADS7263 ADS7223 SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS: ADS7223 All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA = 1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V. ADS7223 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION 12 Bits DC ACCURACY INL Integral nonlinearity –0.5 ±0.2 +0.5 LSB DNL Differential nonlinearity –0.5 ±0.1 +0.5 LSB VOS Input offset error –2 ±0.2 +2 mV VOS match ADC to ADC –1 ±0.1 +1 mV dVOS/dT Input offset thermal drift 1 mV/°C Referenced to the voltage at GERR Gain error –0.1 ±0.01 +0.1 % REFIOx GERR match ADC to ADC –0.1 ±0.005 +0.1 % Referenced to the voltage at GERR/dT Gain error thermal drift 1 ppm/°C REFIOx CMRR Common-mode rejection ratio Both ADCs, dc to 100kHz 92 dB AC ACCURACY SINAD Signal-to-noise + distortion VIN = 5VPP at 10kHz 71 72 dB SNR Signal-to-noise ratio VIN = 5VPP at 10kHz 72 73 dB THD Total harmonic distortion VIN = 5VPP at 10kHz –86 –84 dB SFDR Spurious-free dynamic range VIN = 5VPP at 10kHz 84 86 dB ELECTRICAL CHARACTERISTICS: GENERAL All minimum/maximum specifications at TA = –40°C to +125°C, specified supply voltage range, VREF = 2.5V (int), and tDATA = 1MSPS, unless otherwise noted. Typical values are at TA = +25°C, AVDD = 5V, and DVDD = 3.3V. ADS8363, ADS7263, ADS7223 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT (CHxxP – CHxxN) or CHxx to FSR Full-scale input range –VREF +VREF V CMx VIN Absolute input voltage CHxxx to AGND –0.1 AVDD + 0.1 V CIN Input capacitance CHxxx to AGND 45 pF CID Differential input capacitance 22.5 pF IIL Input leakage current –16 16 nA PSRR Power-supply rejection ratio AVDD = 5.5V 75 dB SAMPLING DYNAMICS Half-clock mode 17.5 tCLK tCONV Conversion time per ADC Full-clock mode 35 tCLK Half-clock mode 2 tCLK tACQ Acquisition time Full-clock Mode 4 tCLK fDATA Data rate 25 1000 kSPS tA Aperture delay 6 ns tA match ADC to ADC 50 ps tAJIT Aperture jitter 50 ps Half-clock mode 0.5 20 MHz fCLK Clock frequency Full-clock mode 1 40 MHz Half-clock mode 50 2000 ns tCLK Clock period Full-clock mode 25 1000 ns 4 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): ADS8363 ADS7263 ADS7223 |
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