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TPS7A6201-Q1 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS7A6201-Q1 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 21 page GND VOUT VIN EN FB 1 2 3 4 5 TPS7A6201-Q1 SLVSAA0B – NOVEMBER 2010 – REVISED MARCH 2012 www.ti.com DEVICE INFORMATION KTT PACKAGE (TOP VIEW) TERMINAL FUNCTIONS NO. NAME TYPE DESCRIPTION Input voltage pin: The unregulated input voltage is supplied to this pin. A bypass capacitor shall be 1 VIN I connected between VIN pin and GND pin to dampen input line transients. Enable pin: This is a high voltage tolerant input pin with an internal pull down. A high input to this pin 2 EN I activates the device and turns the regulator ON. This input can be connected to VIN terminal for self bias applications. If this pin is not connected, the device will stay disabled. 3 GND I/O Ground pin: This is signal ground pin of the IC. Feedback pin: This pin is used to connect external resistors to ground in order to program the output 4 FB I voltage. Regulated output voltage pin: This is a regulated output voltage pin with a limitation on maximum output current. An external resistor divider is connected at this pin to program the output voltage. In order to 5 VOUT O achieve stable operation and prevent oscillation, an external output capacitor (COUT) with low ESR shall be connected between this pin and GND pin. 4 Copyright © 2010–2012, Texas Instruments Incorporated |
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