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LM3502SQX-16NOPB Datasheet(PDF) 3 Page - Texas Instruments |
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LM3502SQX-16NOPB Datasheet(HTML) 3 Page - Texas Instruments |
3 / 28 page LM3502 www.ti.com SNVS339A – SEPTEMBER 2005 – REVISED AUGUST 2006 VOUT1 pin to minimize trace resistance and EMI radiation. Sw (Bump D2): Drain connection of the internal power NMOS FET switch (Figure 4: N1) Minimize the metal trace length and maximize the metal trace width connected to this pin to reduce EMI radiation and trace resistance. PGND (Bump D3): Power ground pin Connect directly to the ground plane. AGND (Bump C3): Analog ground pin Connect the analog ground pin directly to the PGND pin. VIN (Bump B3): Supply or input voltage connection pin The CIN capacitor should be as close to the device as possible, between the VIN pin and ground plane. En2 (Bump A3): Enable pin for the internal NMOS FET switch (Figure 4: N2) during device operation When VEn2 is ≤ 0.3V, the internal NMOS FET switch turns on and the SUB display turns off. When VEn2 is ≥ 1.4V, the internal NMOS FET switch turns off and the SUB display turns on. The En2 pin has an internal pull down resistor, thus the internal NMOS FET switch is normally in the on state of operation with the SUB display turned off. If VEn1 and VEn2 are ≤ 0.3V and VCntrl is ≥ 1.4V, the LM3502 will enter a low IQ shutdown mode of operation where all the internal FET switches are off. If VOUT2 is not used, En2 must be grounded or floating and use En1 along with Cntrl, to enable the device. En1 (Bump A2): Enable pin for the internal PMOS FET switch (Figure 4: P1) during device operation When VEn1 is ≤ 0.3V, the internal PMOS FET switch turns on and the MAIN display is turned off. When VEn1 is ≥ 1.4V, the internal PMOS FET switch turns off and the MAIN display is turned on. The En1 pin has an internal pull down resistor, thus the internal PMOS FET switch is normally in the on state of operation with the MAIN display turned off. If VEn1 and VEn2 are ≤ 0.3V and VCntrl is ≥ 1.4V, the LM3502 will enter a low IQ shutdown mode of operation where all the internal FET switches are off. If VOUT2 is not used, En2 must be grounded and use En1 a long with Cntrl, to enable the device. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Copyright © 2005–2006, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LM3502 |
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