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AMC1210 Datasheet(PDF) 8 Page - Texas Instruments |
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AMC1210 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 54 page  PARALLEL MODE 1 TIMING CHARACTERISTICS (1) AD(7:0) Internaladdress ADDR ADDR ADDR+1 MSB LSB MSB t w1 t w2 t d1 t d2 t w3 t su1 t h1 t su2 t h2 Parallelmode1,writeaccess t w4 CS WR RD ALE ADDR MSB LSB MSB ADDR ADDR+1 AD(7:0) Internaladdress Parallelmode1,readaccess t d3 t d4 t w5 t d5 t d6 t w6 t d7 CS WR RD ALE AMC1210 SBAS372D – APRIL 2006 – REVISED MAY 2009.............................................................................................................................................................. www.ti.com Over recommended operating free-air temperature range at –40°C to +125°C, DVDD = +5V, and BVDD = +2.7V, unless otherwise noted. PARAMETER(2) MIN MAX UNIT tw1 CS low width 40 ns tw2 CS high width 5 ns td1 Delay time from CS low to WR low 3 ns td2 Delay time from WR high to CS high 5 ns tw3 WR low width 10 ns tw4 WR high width 10 ns tsu1 Setup time from ALE high to WR low 0 ns th1 Hold time from WR high to ALE low 2 ns tsu2 Setup time from address valid to WR high 6 ns th2 Hold time from WR high to address invalid 5 ns td3 Delay time from CS low to RD low 0 ns td4 Delay time from RD high to CS high 6 ns tw5 RD low width 30 ns tw6 RD high width 13 ns td5 Delay time from RD low to data valid 30 ns td6 Delay time from RD high to databus in tristate 0 10 ns td7 Delay time from WR high to RD low 10 ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of BVDD) and timed from a voltage level of (VIL + VIH)/2. (2) tw2 is obsolete if CS stays low between the WR and RD pulses. Figure 4. Parallel Mode 1 Timing 8 Submit Documentation Feedback Copyright © 2006–2009, Texas Instruments Incorporated Product Folder Link(s): AMC1210 |
Número de pieza similar - AMC1210_14 |
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Descripción similar - AMC1210_14 |
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