Motor de Búsqueda de Datasheet de Componentes Electrónicos
Selected language     Spanish  ▼
Nombre de pieza

TSB41AB2PAPG4 Datasheet(Hoja de datos) 4 Page - Texas Instruments

Click here to check the latest version.
No. de Pieza. TSB41AB2PAPG4
Descarga  55 Pages
Scroll/Zoom Zoom In 100% Zoom Out
Fabricante  TI1 [Texas Instruments]
Página de inicio

 4 page
background image
description (continued)
The LPS input is considered inactive if it remains low for more than 2.6
µs and is considered active otherwise.
When the TSB41AB2 detects that LPS is inactive, it places the PHY-LLC interface into a low-power reset state
in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however, the
SYSCLK output remains active. If the LPS input remains low for more than 26
µs, the PHY-LLC interface is put
into a low-power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is also
held in the disabled state during hardware reset. The TSB41AB2 continues the necessary repeater functions
required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is
in the reset or disabled state and LPS is again observed active, the PHY initializes the interface and returns it
to normal operation.
When the PHY-LLC interface is in the low-power disabled state, the TSB41AB2 automatically enters a
low-power mode if the port is inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41AB2 disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the port (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBIAS, for example). The lowest power consumption (the
ultralow-power sleep mode) is attained when the port is either disconnected, or disabled with the port interrupt
enable bit cleared. The TSB41AB2 exits the low-power mode when the LPS input is asserted high or when a
port event occurs. This requires that the TSB41AB2 become active in order to respond to the event or to notify
the LLC of the event (for example, incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output becomes
active (and the PHY-LLC interface is initialized and become operative) within 7.3 ms after LPS is asserted high
when the TSB41AB2 is in the low-power mode.
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163-ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or when a PHY interrupt occurs. The PHY deasserts the C/LKON output
when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also deasserts the C/LKON
output when a bus reset occurs unless a PHY interrupt condition exists which would otherwise cause C/LKON
to be active.

Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55 

Datasheet Download

Enlace URL

¿ALLDATASHEET es útil para Ud.?  [ DONATE ]  

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Favorito   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©

Mirror Sites
English :  ,  |   Chinese :  |   German :  |   Japanese :  |   Russian :
Korean :   |   Spanish :  |   French :  |   Italian :  |   Portuguese :  |   Polish :