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TSB12LV01B Datasheet(PDF) 2 Page - Texas Instruments |
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TSB12LV01B Datasheet(HTML) 2 Page - Texas Instruments |
2 / 6 page www.ti.com TSB12LV01B SLLA212 – JUNE 2006 However, there are three restrictions that were not present in the TSB12LV01A device: • The TSB12LV01B may only operate with a 50 MHz host-interface clock (BCLK) if the duty cycle is less than 5% away from the 50-50 point, (i.e., the duty cycle must be within 45-55% inclusive). A 40-60% duty cycle clock is acceptable for host clock frequencies at or below 47 MHz. • The TSB12LV01B does not have bus holder cells on the PHY-link interface. • As a result of removing the bus holder cells, the ISO pin (pin 69) was replaced with a Vcc pin on the TSB12LV01B. This document is not intended to serve as a tutorial on 1394; users are referred to the IEEE 1394-1995 serial bus standard for detailed information regarding the 1394 high-speed serial bus. NOTE: This product is for high-volume applications only. For a complete datasheet or more information contact support@ti.com. 2 Submit Documentation Feedback |
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