ADS1224

SBAS286C − JUNE 2003 − REVISED JANUARY 2009

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3

ELECTRICAL CHARACTERISTICS

All specifications at TA = −40°C to +85°C, AVDD = +5V, DVDD = +5V, fCLK = 2MHz, and VREF = +2.5V, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog Input

Full-scale input voltage

AINP − AINN

±2VREF

V

Absolute input voltage

Buffer off; AINP, AINN with respect to GND

GND − 0.1

AVDD + 0.1

V

Absolute input voltage

Buffer on; AINP, AINN with respect to GND

GND + 0.05

AVDD − 1.5

V

Differential input impedance

Buffer off; fCLK = 2MHz

2.7

M

Ω

Differential input impedance

Buffer on; fCLK = 2MHz

1.2

G

Ω

Common-mode input impedance

Buffer off; fCLK = 2MHz

5.4

M

Ω

System Performance

Resolution

No missing codes

24

Bits

Data rate

120 (fCLK/2MHz)

SPS(1)

Integral nonlinearity (INL)

Buffer off, Differential input signal, end point fit

0.0003

0.0015

Integral nonlinearity (INL)

Buffer on, Differential input signal, end point fit

0.0006

% of FSR

Offset error

Buffer off

20

100

µV

Offset error

Buffer on

20

µV

Offset error drift

Buffer off

0.2

µV/°C

Offset error drift

Buffer on

0.2

µV/°C

Offset error match

Between channels

20

100

µV

Gain error

Buffer off

0.004

0.025

%

Gain error

Buffer on

0.008

%

Gain error drift

Buffer off

0.00003

% of FSR/

°C

Gain error drift

Buffer on

0.00006

% of FSR/

°C

Gain error match

Between channels

0.0005

%

Common-mode rejection

Buffer off, at DC

90

110

dB

Common-mode rejection

Buffer on, at DC

90

110

dB

Analog power-supply rejection

Buffer off, at DC,

± 10% ∆ in AVDD

95

dB

Analog power-supply rejection

Buffer on, at DC,

± 10% ∆ in AVDD

95

dB

Digital power-supply rejection

Buffer off, at DC, DVDD = 2.7V to 5.5V

85

dB

Digital power-supply rejection

Buffer on, at DC, DVDD = 2.7V to 5.5V

85

dB

Noise

0.8

ppm of FSR, rms

Temperature Sensor

Temperature sensor voltage

TA = 25°C

106

mV

Temperature sensor coefficient

360

µV/°C

Voltage Reference Input

Reference input voltage

VREF = VREFP − VREFN

0.5

2.5

AVDD(3)

V

Negative reference input

Buffer off

GND − 0.1

VREFP − 0.5

V

Positive reference input

Buffer off

VREFN + 0.5

AVDD + 0.1

V

Negative reference input

Buffer on

GND + 0.05

VREFP − 0.5

V

Positive reference input

Buffer on

VREFN + 0.5

AVDD − 1.5

V

Voltage reference impedance

fCLK = 2MHz

500

k

Ω

(1) SPS = samples per second.

(2) FSR = full-scale range = 4VREF.

(3) It will not be possible to reach the digital output full-scale code when VREF > AVDD/2.