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ADS6425IRGCT Datasheet(PDF) 1 Page - Texas Instruments |
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ADS6425IRGCT Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 60 page  1 FEATURES APPLICATIONS DESCRIPTION ADS6425 www.ti.com ......................................................................................................................................................... SLWS197B – MARCH 2007 – REVISED JUNE 2009 QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE • Base-Station IF Receivers • Maximum Sample Rate: 125 MSPS • Diversity Receivers • 12-Bit Resolution with No Missing Codes • Medical Imaging • 1.65-W Total Power • Test Equipment • Simultaneous Sample and Hold • 70.3 dBFS SNR at Fin = 50 MHz • 83 dBc SFDR at Fin = 50 MHz, 0 dB Gain The ADS6425 is a high performance 12-bit, • 79 dBc SFDR at Fin = 170 MHz, 3.5 dB Gain 125-MSPS quad channel ADC. Serial LVDS data • 3.5 dB Coarse Gain and up to 6 dB outputs reduce the number of interface lines, resulting Programmable Fine Gain for SFDR/SNR in a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The Trade-Off device includes a 3.5 dB coarse gain option that can • Serialized LVDS Outputs with Programmable be used to improve SFDR performance with little Internal Termination Option degradation in SNR. In addition to the coarse gain, • Supports Sine, LVCMOS, LVPECL, LVDS Clock fine gain options also exist, programmable in 1dB Inputs and Amplitude Down to 400 mVpp steps up to 6dB. Differential The output interface is 2-wire, where each ADC's • Internal Reference with External Reference data is serialized and output over two LVDS pairs. Support This makes it possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less • No External Decoupling Required for than 1Gbps easing receiver design. The ADS6425 References also includes the traditional 1-wire interface that can • 3.3-V Analog and Digital Supply be used at lower sampling frequencies. • 64 QFN Package (9 mm × 9 mm) An internal phase locked loop (PLL) multiplies the • Pin Compatible 14-Bit Family (ADS644X - incoming ADC sampling clock to derive the bit clock. SLAS532) The bit clock is used to serialize the 12-bit data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The LVDS output buffers have features such as programmable LVDS currents, current doubling modes, and internal termination options. These can be used to widen eye-openings and improve signal integrity, easing capture by the receiver. The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary. The ADS6425 has internal references, but can also support an external reference mode. The device is specified over the industrial temperature range (–40°C to 85°C). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2007–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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