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ADS6442 Datasheet(PDF) 1 Page - Texas Instruments

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No. de pieza ADS6442
Descripción Electrónicos  QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
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ADS6442 Datasheet(HTML) 1 Page - Texas Instruments

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ADS6445, ADS6444
ADS6443, ADS6442
www.ti.com
SLAS531B – MAY 2007 – REVISED DECEMBER 2009
QUAD CHANNEL, 14-BIT, 125/105/80/65 MSPS ADC WITH SERIAL LVDS OUTPUTS
Check for Samples: ADS6445, ADS6444, ADS6443, ADS6442
1
FEATURES
Pin Compatible 12-Bit Family (ADS642X -
SLAS532A)
Maximum Sample Rate: 125 MSPS
Feature Compatible Dual Channel Family
14-Bit Resolution with No Missing Codes
(ADS624X - SLAS542A, ADS644X - SLAS543A)
Simultaneous Sample and Hold
3.5dB Coarse Gain and up to 6dB
APPLICATIONS
Programmable Fine Gain for SFDR/SNR
Base-Station IF Receivers
Trade-Off
Diversity Receivers
Serialized LVDS Outputs with Programmable
Medical Imaging
Internal Termination Option
Test Equipment
Supports Sine, LVCMOS, LVPECL, LVDS Clock
Inputs and Amplitude down to 400 mVPP
Table 1. ADS64XX Quad Channel Family
Internal Reference with External Reference
125 MSPS
105 MSPS
80 MSPS
65 MSPS
Support
ADS644X
ADS6445
ADS6444
ADS6443
ADS6442
No External Decoupling Required for
14 Bit
References
ADS642X
ADS6425
ADS6424
ADS6423
ADS6422
12 Bit
3.3-V Analog and Digital Supply
64 QFN Package (9 mm × 9 mm)
Table 2. Performance Summary
ADS6445
ADS6444
ADS6443
ADS6442
Fin = 10MHz (0 dB gain)
87
91
92
93
SFDR, dBc
Fin = 170MHz (3.5 dB gain)
79
83
84
84
Fin = 10MHz (0 dB gain)
73.4
73.4
74.2
74.3
SINAD, dBFS
Fin = 170MHz (3.5 dB gain)
68.3
69.3
69.4
70
Power, per channel, mW
420
340
300
265
DESCRIPTION
The ADS6445/ADS6444/ADS6443/ADS6442 (ADS644X) is a family of high performance 14-bit 125/105/80/65
MSPS quad channel A-D converters. Serial LVDS data outputs reduce the number of interface lines, resulting in
a compact 64-pin QFN package (9 mm × 9 mm) that allows for high system integration density. The device
includes 3.5dB coarse gain option that can be used to improve SFDR performance with little degradation in SNR.
In addition to the coarse gain, fine gain options also exist, programmable in 1dB steps up to 6dB.
The output interface is 2-wire, where each ADC data is serialized and output over two LVDS pairs. This makes it
possible to halve the serial data rate (compared to a 1-wire interface) and restrict it to less than 1Gbps easing
receiver design. The ADS644X also includes the traditional 1-wire interface that can be used at lower sampling
frequencies.
An internal phase lock loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock. The bit
clock is used to serialize the 14-bit data from each channel. In addition to the serial data streams, the frame and
bit clocks are also transmitted as LVDS outputs.
The LVDS output buffers have features such as programmable LVDS currents, current doubling modes and
internal termination options. These can be used to widen eye-openings and improve signal integrity, easing
capture by the receiver.
The ADC channel outputs can be transmitted either as MSB or LSB first and 2s complement or straight binary.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007–2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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