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ADS62P23IRGCR Datasheet(PDF) 9 Page - Texas Instruments |
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ADS62P23IRGCR Datasheet(HTML) 9 Page - Texas Instruments |
9 / 78 page ADS62P24, ADS62P25 ADS62P22, ADS62P23 www.ti.com SLAS576C – OCTOBER 2007 – REVISED OCTOBER 2011 TIMING CHARACTERISTICS – LVDS AND CMOS MODES (1) (continued) Typical values are specified at 25 °C, AVDD = DRVDD = 3.3 V, maximum rated sampling frequency, sine wave input clock, 1.5 VPP clock amplitude, CL = 5 pF (2), I O = 3.5 mA, RL = 100 Ω (3), no internal termination, unless otherwise noted. Min and max values are specified across the full temperature range TMIN = –40°C to TMAX = 85°C, AVDD = 3.0 V to 3.6 V, unless otherwise specified. ADS62P25 ADS62P24 ADS62P23 ADS62P22 FS = 125 MSPS FS = 105 MSPS FS = 80 MSPS FS = 65 MSPS PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX PARALLEL CMOS MODE, DRVDD = 2.5 V to 3.6 V, default output buffer drive strength (7) Data valid(9) to 50% Data setup tsu of CLKOUT rising 2.0 3.5 2.8 4.3 4.3 5.8 5.7 7.2 ns time(8) edge 50% of CLKOUT Data hold th rising edge to data 2.0 3.5 2.7 4.2 4.2 5.7 5.6 7.1 ns time(8) becoming invalid(9) Input clock rising Clock edge zero-cross to tPDI propagation 5.8 7.3 8.8 5.8 7.3 8.8 5.8 7.3 8.8 5.8 7.3 8.8 ns 50% of CLKOUT delay rising edge Duty cycle of output Output clock (CLKOUT) clock duty 45% 53% 60% 45% 53% 60% 45% 53% 60% 45% 53% 60% 10 ≤ Fs ≤ 125 cycle MSPS Rise time measured from 20% to 80% of Data rise DRVDD tr time Fall time measured 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns tf Data fall from 80% to 20% of time DRVDD 1 ≤ Fs ≤ 125 MSPS Rise time measured Output from 20% to 80% of clock rise DRVDD tCLKRISE time Fall time measured 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 1.0 1.8 2.5 ns tCLKFALL Output from 80% to 20% of clock fall DRVDD time 1 ≤ Fs ≤ 125 MSPS PARALLEL CMOS INTERFACE, DRVDD = 1.8 V, maximum buffer drive strength (10) Input clock rising edge tSTART to data 8.5 7.5 5.5 3.6 ns valid (11) (12) Width of tDV valid data 3.3 6.0 5.0 7.5 8.0 10.5 10.5 13.5 ns window (7) For DRVDD < 2.2 V, it is recommended to use external clock for data capture and NOT the device output clock signal (CLKOUT). See Parallel CMOS interface in application section. (8) Setup and hold time specifications take into account the effect of jitter on the output data and clock. (9) Data valid refers to logic high of 2 V (1.7 V) and logic low of 0.8 V (0.7 V) for DRVDD = 3.3 V (2.5 V). (10) For DRVDD < 2.2 V, output clock cannot be used for data capture. A delayed version of the input clock can be used, that gives the desired setup and hold times at the receiving chip. (11) Data valid refers to logic high of 1.26V and logic low of 0.54V for DRVDD = 1.8V. (12) Measured from zero-crossing of input clock having 50% duty cycle. Copyright © 2007–2011, Texas Instruments Incorporated 9 |
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