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ADS7882 Datasheet(PDF) 6 Page - Texas Instruments |
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ADS7882 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 30 page PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 BUSY BDGND +VBD NC NC NC NC DB0 DB1 DB2 DB3 BDGND REFIN REFOUT NC +VA AGND +IN −IN AGND +VA +VA AGND AGND NC − No connection ADS7882 SLAS630 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. PFB 8-BIT BUS 16-BIT BUS DATA BUS BYTE = 0 BYTE = 1 BYTE = 0 DB11 16 O D11 (MSB) D3 D11 (MSB) DB10 17 O D10 D2 D10 DB9 18 O D9 D1 D9 DB8 19 O D8 D0 (LSB) D8 DB7 20 O D7 0 D7 DB6 21 O D6 0 D6 DB5 22 O D5 0 D5 DB4 23 O D4 0 D4 DB3 26 O D3 0 D3 DB2 27 O D2 0 D2 DB1 28 O D1 0 D1 DB0 29 O D0 (LSB) 0 D0 (LSB) CONTROL PINS Chip select. Active low signal enables chip operation like acquisition start, conversion start, bus CS 42 I release from 3-state. Refer to the timing diagrams for more details. Conversion start. The rising edge starts the acquisition. The falling edge of this input ends the CONVST 40 I acquisition and starts the conversion. Refer to the timing diagrams for more details. Active low synchronization pulse for the parallel output. When CS is low, this serves as the RD 41 I output enable and puts the previous conversion results on the bus. A_PWD 37 I Nap mode enable, active low 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS7882 |
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