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ADS7812PBG4 Datasheet(PDF) 4 Page - Texas Instruments

No. de pieza ADS7812PBG4
Descripción Electrónicos  Low-Power, Serial 12-Bit Sampling ANALOG-TO-DIGITAL CONVERTER
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS7812PBG4 Datasheet(HTML) 4 Page - Texas Instruments

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ADS7812
4
SBAS042A
www.ti.com
PIN CONFIGURATION
PIN CONFIGURATION
Top View
DIP, SOIC
V
S
PWRD
BUSY
CS
CONV
EXT/INT
DATA
DATACLK
R1
IN
GND
R2
IN
R3
IN
BUF
CAP
REF
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADS7812
ANALOG
CONNECT
CONNECT
CONNECT
INPUT
INPUT
R1IN
R2IN
R3IN
IMPEDANCE
RANGE (V)
TO
TO
TO
(k
Ω)
±10V
VIN
BUF
GND
45.7
0.3125V to
2.8125V
VIN
VIN
VIN
> 10,000
±5V
GND
BUF
VIN
26.7
0V to 10V
BUF
GND
VIN
26.7
0V to 4V
BUF
VIN
GND
21.3
±3.33V
VIN
BUF
VIN
21.3
0.5V to
4.5V
GND
VIN
GND
21.3
TABLE I. ADS7812 Input Ranges.
PIN #
NAME
DESCRIPTION
1R1IN
Analog Input. See Tables I and IV.
2
GND
Ground
3R2IN
Analog Input. See Tables I and IV.
4R3IN
Analog Input. See Tables I and IV.
5
BUF
Reference Buffer Output. Connect to R1IN, R2IN, or R3IN, as needed.
6
CAP
Reference Buffer Compensation Node. Decouple to ground with a 1
µF tantalum capacitor in parallel with a 0.01µF ceramic capacitor.
7
REF
Reference Input/Output. Outputs internal +2.5V reference via a series 4k
Ω resistor. Decouple this voltage with a 1µF to 2.2µF
tantalum capacitor to ground. If an external reference voltage is applied to this pin, it will override the internal reference.
8
GND
Ground
9
DATACLK
Data Clock Pin. With EXT/INT LOW, this pin is an output and provides the synchronous clock for the serial data. The output
is tri-stated when CS is HIGH. With EXT/INT HIGH, this pin is an input and the serial data clock must be provided externally.
10
DATA
Serial Data Output. The serial data is always the result of the last completed conversion and is synchronized to DATACLK.
If DATACLK is from the internal clock (EXT/INT LOW), the serial data is valid on both the rising and falling edges of DATACLK.
DATA is tri-stated when CS is HIGH.
11
EXT/INT
External or Internal DATACLK Pin. Selects the source of the synchronous clock for serial data. If HIGH, the clock must be
provided externally. If LOW, the clock is derived from the internal conversion clock. Note that the clock used to time the
conversion is always internal regardless of the status of EXT/INT.
12
CONV
Convert Input. A falling edge on this input puts the internal sample/hold into the hold state and starts a conversion regardless
of the state of CS. If a conversion is already in progress, the falling edge is ignored. If EXT/INT is LOW, data from the previous
conversion will be serially transmitted during the current conversion.
13
CS
Chip Select. This input tri-states all outputs when HIGH and enables all outputs when LOW. This includes DATA, BUSY, and
DATACLK (when EXT/INT is LOW). Note that a falling edge on CONV will initiate a conversion even when CS is HIGH.
14
BUSY
Busy Output. When a conversion is started, BUSY goes LOW and remains LOW throughout the conversion. If EXT/INT is
LOW, data is serially transmitted while BUSY is LOW. BUSY is tri-stated when CS is HIGH.
15
PWRD
Power Down Input. When HIGH, the majority of the ADS7812 is placed in a low power mode and power consumption is
significantly reduced. CONV must be taken LOW prior to PWRD going LOW in order to achieve the lowest power
consumption. The time required for the ADS7812 to return to normal operation after power down depends on a number of
factors. Consult the Power Down section for more information.
16
VS
+5V Supply Input. For best performance, decouple to ground with a 0.1
µF ceramic capacitor in parallel with a 10µF tantalum
capacitor.


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