ADS901

8

SBAS054A

402

Ω

A1

V

IN

402

Ω

R

1

1k

Ω

V

CM

C

1

0.1

µF

0.1

µF

IN

CM

+5V

R

1

50

Ω

–5V

+3V

ADS901

THEORY OF OPERATION

The ADS901 is a high speed sampling analog-to-digital

converter that utilizes a pipeline architecture. The fully

differential topology and digital error correction guarantee

10-bit resolution. The differential track/hold circuit is shown

in Figure 1. The switches are controlled by an internal clock

which has a non-overlapping two phase signal,

φ1 and φ2. At

the sampling time the input signal is sampled on the bottom

plates of the input capacitors. In the next clock phase,

φ1, the

bottom plates of the input capacitors are connected together

and the feedback capacitors are switched to the op amp

is a held DC representation of the analog input at the sample

time. The track/hold circuit can also convert a single-ended

input signal into a fully differential signal for the quantizer.

Consequently, the input signal-to-noise performance. Other

parameters such as small-signal and full-power bandwidth,

and wideband noise are also defined in this stage.

To accommodate a bipolar signal swing, the ADS901 oper-

from the external references. Due to the symmetric resistor

top and bottom reference voltage. Equation (1) can be used

for calculating the common-mode voltage level.

(1)

There is a 5.0 clock cycle data latency from the start convert

signal to the valid output data. The standard output coding

is Straight Offset Binary where a full scale input signal

corresponds to all “1’s” at the output. The digital outputs of

the ADS901 can be set to a high impedance state by driving

the three-state (pin 16) with a logic “HI”. Normal operation

is achieved with pin 16 “LO” or Floating due to internal

pull-down resistors. This function is provided for testability

purposes but is not recommended to be used dynamically.

APPLICATIONS

SIGNAL SWING AND COMMON-MODE

CONSIDERATIONS

The ADS901 is designed to operate on a +3V single supply

voltage. The nominal input signal swing is 1Vp-p, situated

between +1V and +2V. This means that the signal swings

±0.5V around a common-mode voltage of +1.5V, which is

it might be advantageous to increase the input signal swing.

This will improve the achievable signal-to-noise perfor-

mance. However, considerations should be made to keep the

signal swing within the linear range of operation of the

driving circuitry to avoid any excessive distortion. In ex-

treme situations the performance of the converter will start

to degrade due to variations of the input’s switch on-

resistance over the input voltage. Therefore, the signal swing

should remain approximately 0.5V away from each rail

during normal operation.

DRIVING THE ANALOG INPUTS

AC-COUPLED DRIVER

Figure 2 shows an example of an ac-coupled, single-ended

interface circuit using a high-speed op amp that operates on

φ1

φ1

φ2

φ1

φ1

φ1

φ1

φ1

φ2

φ1

φ2

φ1

φ2

IN

IN

OUT

OUT

Op Amp

Bias

V

CM

Op Amp

Bias

V

CM

C

H

C

I

C

I

C

H

Input Clock (50%)

Internal Non-overlapping Clock

FIGURE 1. Input Track/Hold Configuration with Timing

Signals.

The pipelined quantizer architecture has 9 stages with each

stage containing a two-bit quantizer and a two bit digital-

to-analog converter, as shown in Figure 2. Each two-bit

quantizer stage converts on the edge of the sub-clock, which

is the same frequency of the externally applied clock. The

output of each quantizer is fed into its own delay line to

time-align it with the data created from the following quan-

tizer stages. This aligned data is fed into a digital error

correction circuit which can adjust the output data based on

the information found on the redundant bits. This technique

provides the ADS901 with excellent differential linearity

and guarantees no missing codes at the 10-bit level.

FIGURE 2. AC-Coupled, Single-Ended Interface Circuit.