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ADS574JU Datasheet(PDF) 9 Page - Texas Instruments |
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ADS574JU Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 17 page  9 ® ADS574 FIGURE 3. R/C Pulse Low—Outputs Enabled After Conver- sion. FIGURE 4. R/C Pulse High — Outputs Enabled Only While R/C Is High. S/H CONTROL MODE AND ADC574 EMULATION MODE The basic difference between these two modes is the assumptions about the state of the input signal both before and during the conversion. The differences are shown in Figure 9 and Table VI. In the Control Mode it is assumed that during the required 4 µs acquisition time the signal is not slewing faster than the slew rate of the ADS574. No assumption is made about the input level after the convert command arrives, since the input signal is sampled and conversion begins immediately after the convert command. This means that a convert command can also be used to switch an input multiplexer or change gains on a program- mable gain amplifier, allowing the input signal to settle before the next acquisition at the end of the conversion. Because aperture jitter is minimized by the internal sample/ hold circuit, a high input frequency can be converted without an external sample/hold. In the Emulation Mode, no assumption is made about the input signal prior to the convert command. A delay time is introduced between the convert command and the start of conversion to allow the ADS574 enough time to acquire the input signal before converting. The delay increases the effective aperture time from 0.02 µs to 4µs, but allows the ADS574 to replace the ADC574 in any circuit. Any slewing of the analog input prior to the convert command in existing SYMBOL PARAMETER MIN TYP MAX UNITS Convert Mode tDSC STS delay from CE 60 200 ns tHEC CE Pulse width 50 30 ns tSSC CS to CE setup 50 20 ns tHSC CS low during CE high 50 20 ns tSRC R/C to CE setup 50 0 ns tHRC R/C low during CE high 50 20 ns tSAC AO to CE setup 0 ns tHAC AO valid during CE high 50 20 ns Read Mode tDD Access time from CE 75 150 ns tHD Data valid after CE low 25 35 ns tHL Output float delay 100 150 ns tSSR CS to CE setup 50 0 ns tSRR R/C to CE setup 0 ns tSAR AO to CE setup 50 25 ns tHSR CS valid after CE low 0 ns tHRR R/C high after CE low 0 ns tHAR AO valid after CE low 50 ns tHS STC delay after data valid 300 400 1000 SYMBOL PARAMETER MIN TYP MAX UNITS tHRL Low R/C Pulse Width 25 ns tDS STS Delay from R/C 200 ns tHDR Data Valid After R/C Low 25 ns tHRH High R/C Pulse Width 100 ns tDDR Data Access Time 150 ns TABLE IV. Stand-Alone Mode Timing. (TA = TMIN to TMAX ). TABLE V. Timing Specifications, Fully Controlled Operation. (T A = TMIN to TMAX ). R/C DB11-DB0 Status Data Valid Data Valid High-Z-State t HRL t DS t C t HDR t HS R/C DB11-DB0 Status Data Valid High-Z-State t HRH t DS t C t DDR High-Z t HDR |
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