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ADS1245IDGSTG4 Datasheet(PDF) 11 Page - Texas Instruments |
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ADS1245IDGSTG4 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 23 page  ADS1245 SBAS287A − JUNE 2003 − REVISED SEPTEMBER 2003 www.ti.com 11 DATA FORMAT The ADS1245 outputs 24 bits of data in Binary Two’s Complement format. The least significant bit (LSB) has a weight of (2VREF)/(223 − 1). A positive full-scale input produces an output code of 7FFFFFh and the negative full-scale input produces an output code of 8000000h. The output clips at these codes for signals exceeding full-scale. Table 1 summarizes the ideal output codes for different input signals. Table 1. Ideal Output Code vs Input Signal INPUT SIGNAL VIN (AINP − AINN) IDEAL OUTPUT CODE(1) ≥ +2VREF 7FFFFFH ) 2V REF (223) * 1 000001H 0 000000H * 2V REF (223) * 1 FFFFFFH v* 2V REF 223 (223) * 1 800000H NOTE: (1) Excludes effects of noise, INL, offset, and gain errors. DATA RETRIEVAL The ADS1245 continuously converts the analog input signal. To retrieve data, wait until DRDY/DOUT goes low, as shown in Figure 24. After this occurs, begin shifting out the data by applying SCLKs. Data is shifted out most significant bit (MSB) first. It is not required to shift out all the 24 bits of data, but the data must be retrieved before the new data is updated (see t3) or else it will be overwritten. Avoid data retrieval during the update period. DRDY/DOUT remains at the state of the last bit shifted out until it is taken high (see t7), indicating that new data is being updated. To avoid having DRDY/DOUT remain in the state of the last bit, shift a 25th SCLK to force DRDY/DOUT high; see Figure 25. This technique is useful when a host controlling the ADS1245 is polling DRDY/DOUT to determine when data is ready. DRDY/DOUT 23 22 21 124 0 LSB MSB Data Data is ready. SCLK t3 t 8 t4 t 4 t7 New data is ready. t5 t6 SYMBOL DESCRIPTION MIN MAX UNITS (1) Load on DRDY/DOUT = 20pF||100k Ω. (2) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK period. For example, for fCLK = 4.9152MHz, t8 →33.333ms. t3 t4 t5 (1) t6 t7 t8 (2) DRDY/DOUT low to first SCLK rising edge. SCLK positive or negative pulse width. SCLK rising edge to new data bit valid; propagation delay. SCLK rising edge to old data bit valid: hold time. Data updating, no read back allowed. Conversion time (1/data rate). 0 100 50 0 152 66.667 152 66.667 ns ns ns ms ns µs NOTES: Figure 24. Data Retrieval Timing |
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