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ADS1281 Datasheet(PDF) 10 Page - Texas Instruments |
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ADS1281 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 51 page 4th-Order DS Modulator Programmable DigitalFilter Serial Interface Calibration Control AINP AVDD AVSS DVDD CLK DGND HPF/SYNC AINN VREFN MFLAG VREFP ADS1281 RESET PINMODE PWDN Over-Range Detection MOD/DIN DOUT DRDY SCLK LDO +1.8V (DigitalCore) BYPAS ADS1281 SBAS378D – AUGUST 2007 – REVISED JUNE 2010 www.ti.com OVERVIEW The ADS1281 is a high-performance analog-to-digital The digital filter is comprised of a variable decimation converter (ADC) intended for energy exploration, rate, fifth-order sinc filter followed by a seismic monitoring, chromatography, and other decimate-by-32, FIR low-pass filter with exacting applications. The converter provides 24- or programmable phase, and then by an adjustable 32-bit output data in data rates from 4000SPS to high-pass filter for dc removal of the output reading. 250SPS. The output of the digital filter can be taken from the sinc, the FIR low-pass, or the IIR high-pass section. Figure 19 shows the block diagram of the ADS1281. The device features unipolar and bipolar analog Gain and offset registers scale the digital filter output power supplies (AVDD and AVSS, respectively) for to produce the final code value. The scaling feature input range flexibility and a digital supply accepting can be used for calibration and sensor gain matching. 1.8V to 3.3V. The analog supplies may be set to +5V The output data are provided with either a 24-bit word to accept unipolar signals (with input offset) or set or a full 32-bit word, allowing full utilization of the lower in the range of ±2.5V to accept true bipolar inherently high resolution. input signals (ground referenced). The PINMODE input pin determines the mode of the An internal low-dropout (LDO) regulator is used to device: Pin control or Register control. In Pin control power the digital core from DVDD. The BYPAS pin is mode, the device is controlled by simple pin settings; the LDO output and requires a 0.1mF capacitor for there are no registers to program. In Register control noise reduction (BYPAS should not be used to drive mode, the device is controlled by register settings. external circuitry). The functionality of several device pins depends on the control mode selected (see the Pin and Register The inherently-stable, fourth-order, ΔΣ modulator Modes section). measures the differential input signal VIN = (AINP – AINN) against the differential reference The SYNC input resets the operation of both the VREF = (VREFP – VREFN). A digital output (MFLAG) digital filter and the modulator, allowing synchronized indicates that the modulator is in over-range resulting conversions of multiple ADS1281 devices to an from an input overdrive condition. The modulator external event. The SYNC input supports a output is available directly on the MCLK, M0, and M1 continuously-toggled input mode that accepts an output pins. The modulator connects to an on-chip external data frame clock locked to an integer of the digital filter that provides the output code readings. conversion rate. Figure 19. ADS1281 Block Diagram 10 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated Product Folder Link(s): ADS1281 |
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